Module 4: Combinational Logic Circuits

Comprehensive Academic Reference Guide for Computer Engineering (TU / IOE Syllabus)

4.1 Design Procedures for Combinational Logic Circuits

A Combinational Logic Circuit is a type of digital circuit whose output at any given instant depends strictly and solely on the present combination of inputs. Unlike sequential circuits, combinational circuits contain no memory elements (flip-flops), no internal state storage, and no feedback loops.

Fundamental Characteristic

For $N$ input variables, there are $2^N$ possible binary input combinations. For each combination, there is exactly one possible output state defined by the logic equations: $Y_j = f_j(X_0, X_1, \dots, X_{N-1})$.

4.1.1 Standard 5-Step Design Methodology

Problem Specification: Clearly state the real-world operational requirements, identify all input variables, and define required output signals.
Variable Assignment & Input/Output Mapping: Assign distinct algebraic letter symbols (e.g., $A, B, C$ for inputs; $S, C, Y$ for outputs) to all input and output lines.
Truth Table Construction: Construct a complete truth table listing all $2^N$ input combinations alongside their required output logic states ($0, 1,$ or Don't Care $X$).
Boolean Function Simplification: Derive algebraic expressions for each output using Karnaugh Maps (K-Maps), Quine-McCluskey, or Boolean postulates to achieve minimal Sum-of-Products (SOP) or Product-of-Sums (POS).
Logic Circuit Realization & Verification: Draw the final gate-level schematic diagram using target logic gates (AND/OR/NOT, XOR, or Universal NAND/NOR gates) and verify correct logical functionality.

4.2 Half-Adder and Full-Adder

4.2.1 Half-Adder (HA)

A Half-Adder is a combinational circuit that performs the arithmetic addition of two single binary bits ($A$ and $B$). It generates two outputs: Sum ($S$) and Carry ($C$).

Inputs		Outputs		Arithmetic Operation ($A + B$)
A	B	Carry (C)	Sum (S)	Arithmetic Operation ($A + B$)
0	0	0	0	$0 + 0 = 0_10$ (Carry 0, Sum 0)
0	1	0	1	$0 + 1 = 1_10$ (Carry 0, Sum 1)
1	0	0	1	$1 + 0 = 1_10$ (Carry 0, Sum 1)
1	1	1	0	$1 + 1 = 2_10 = 10_2$ (Carry 1, Sum 0)

Derived Equations:

Sum ($S$): $\bar{A}B + A\bar{B} = A \oplus B$ (XOR Gate)
Carry ($C$): $A B$ (AND Gate)

Half-Adder Gate Level Schematic

   A ────┬───────────────[ XOR ]─────── Sum (S = A ⊕ B)
         │              /
   B ────┼──────┬──────/
         │      │
         └──────┼────────[ AND ]─────── Carry (C = A · B)
                └───────/

4.2.2 Full-Adder (FA)

A Full-Adder performs arithmetic addition of three single binary bits: two input bits ($A, B$) and an incoming carry bit ($C_{in}$) from a previous lower-significant bit stage.

Inputs			Outputs		Decimal Sum ($A + B + C_{in}$)
A	B	C_in	C_out	Sum (S)	Decimal Sum ($A + B + C_{in}$)
0	0	0	0	0	0
0	0	1	0	1	1
0	1	0	0	1	1
0	1	1	1	0	2 ($10_2$)
1	0	0	0	1	1
1	0	1	1	0	2 ($10_2$)
1	1	0	1	0	2 ($10_2$)
1	1	1	1	1	3 ($11_2$)

K-Map Minimization for Full Adder

K-Map for Sum ($S = \sum m(1,2,4,7)$)

A\BC_in	00	01	11	10
0	0	1	0	1
1	1	0	1	0

Checkerboard pattern $\implies S = A \oplus B \oplus C_{in}$

K-Map for Carry Out ($C_{out} = \sum m(3,5,6,7)$)

A\BC_in	00	01	11	10
0	0	0	1	0
1	0	1	1	1

Three Quads/Pairs $\implies C_{out} = A B + B C_{in} + A C_{in}$

4.2.3 Implementation of Full-Adder using Two Half-Adders and an OR Gate

We can factor the Carry expression into: $C_{out} = A B + C_{in}(A \oplus B)$. This allows direct modular cascade implementation:

HA₁ Outputs: S₁ = A ⊕ B , C₁ = A · B First Half-Adder

HA₂ Inputs: S₁ and C_in Feeding intermediate sum to HA₂

HA₂ Outputs: S = S₁ ⊕ C_in = A ⊕ B ⊕ C_in Final Full-Adder Sum Output

HA₂ Carry: C₂ = S₁ · C_in = (A ⊕ B) C_in Second Half-Adder Carry

Final C_out = C₁ + C₂ = A B + C_in(A ⊕ B) OR Gate combining carries

Full-Adder using 2 Half-Adders & 1 OR Gate

  A ───┬─────────┐
       │   HA1   │─── S1 (A⊕B) ──────┬─────────┐
  B ───┴─────────┘                   │   HA2   │────── Sum (S = A ⊕ B ⊕ Cin)
               │ C1 (AB)             │         │
               │                     └─────────┘
  Cin ─────────┼──────────────────────────┘  │ C2 = Cin(A⊕B)
               │                             │
               └───────────────[ OR ]────────┴──────── Carry Out (Cout)
                              /

4.3 Half-Subtractor and Full-Subtractor

4.3.1 Half-Subtractor (HS)

A Half-Subtractor subtracts bit $B$ from bit $A$ ($A - B$) and yields two outputs: Difference ($D$) and Borrow ($B_{out}$).

Inputs		Outputs		Subraction Operation ($A - B$)
A	B	Borrow (B_out)	Difference (D)	Subraction Operation ($A - B$)
0	0	0	0	$0 - 0 = 0$
0	1	1	1	$0 - 1 = -1 \implies 2 - 1 = 1$ (Borrow 1)
1	0	0	1	$1 - 0 = 1$
1	1	0	0	$1 - 1 = 0$

Equations: Difference $D = A \oplus B$, Borrow $B_{out} = \bar{A} B$.

4.3.2 Full-Subtractor (FS)

A Full-Subtractor calculates $A - B - B_{in}$, incorporating an incoming borrow $B_{in}$.

Inputs			Outputs		Operation Logic
A	B	B_in	B_out	Difference (D)	Operation Logic
0	0	0	0	0	$0 - 0 - 0 = 0$
0	0	1	1	1	$0 - 0 - 1 = -1 \implies D=1, B_{out}=1$
0	1	0	1	1	$0 - 1 - 0 = -1 \implies D=1, B_{out}=1$
0	1	1	1	0	$0 - 1 - 1 = -2 \implies D=0, B_{out}=1$
1	0	0	0	1	$1 - 0 - 0 = 1 \implies D=1, B_{out}=0$
1	0	1	0	0	$1 - 0 - 1 = 0 \implies D=0, B_{out}=0$
1	1	0	0	0	$1 - 1 - 0 = 0 \implies D=0, B_{out}=0$
1	1	1	1	1	$1 - 1 - 1 = -1 \implies D=1, B_{out}=1$

Full Subtractor Derived Equations:

Difference ($D$): $A \oplus B \oplus B_{in}$
Borrow Out ($B_{out}$): $\bar{A}B + \bar{A}B_{in} + BB_{in} = \bar{A}B + B_{in}(\overline{A \oplus B})$

Full Subtractor using 2 Half-Subtractors & 1 OR Gate

HS₁ produces $D_1 = A \oplus B$ and $B_1 = \bar{A}B$.
HS₂ takes $D_1$ and $B_{in}$ to produce $D = D_1 \oplus B_{in} = A \oplus B \oplus B_{in}$ and $B_2 = \bar{D_1} B_{in} = (\overline{A \oplus B}) B_{in}$.
Combining borrows through an OR gate yields: $B_{out} = B_1 + B_2 = \bar{A}B + B_{in}(\overline{A \oplus B})$.

4.3.3 Unified 4-Bit Adder-Subtractor Circuit

By connecting an XOR gate to each $B$ input bit with a control line $M$ (Mode), a single circuit acts as an Adder when $M=0$ and a Subtractor when $M=1$ (leveraging 2's complement $A - B = A + \bar{B} + 1$).

4-Bit Parallel Adder / Subtractor Unit

Mode Control (M) ────┬────────────────────────────────────────── C0 (Injected Carry)
                     │
         ┌───────────┼───────────┬───────────┐
         │           │           │           │
       [XOR]       [XOR]       [XOR]       [XOR]
         │ B0        │ B1        │ B2        │ B3
         ▼           ▼           ▼           ▼
       ┌───┐ C1    ┌───┐ C2    ┌───┐ C3    ┌───┐ C4 (Overflow/Carry)
 A0 ──►│FA0│──────►│FA1│──────►│FA2│──────►│FA3│──────► Cout
       └───┘       └───┘       └───┘       └───┘
         │ S0        │ S1        │ S2        │ S3
                 Outputs (S = A + B if M=0; S = A - B if M=1)

4.4 Ripple Carry Adders and Fast Adders

4.4.1 N-Bit Ripple Carry Adder (RCA)

A Ripple Carry Adder is constructed by cascading $N$ Full Adders in series. The carry output $C_{i+1}$ from stage $i$ is connected directly to the carry input $C_i$ of stage $i+1$.

The Ripple Propagation Delay Bottleneck

In an $N$-bit Ripple Carry Adder, bit $N-1$ cannot calculate its correct sum until the carry ripples through all preceding $N-1$ stages. If each Full-Adder stage has propagation delay $T_{FA}$ (typically 2 gate delays), the total delay for an $N$-bit addition is:

T_total = N × T_FA = 2N Gate Delays

For 32-bit or 64-bit ALUs, this propagation delay causes significant performance penalties.

4.4.2 Fast Adder: Carry Lookahead Adder (CLA)

To eliminate ripple delays, a Carry Lookahead Adder (CLA) generates all carry signals simultaneously in parallel using high-speed lookahead logic gates.

Derivation of CLA Equations:

For any stage $i$ of an adder, define two signals:

Carry Generate ($G_i$): $G_i = A_i \cdot B_i$ (Stage generates a carry regardless of incoming carry)
Carry Propagate ($P_i$): $P_i = A_i \oplus B_i$ (Stage propagates incoming carry to next stage)

The Sum output is $S_i = P_i \oplus C_i$, and the Carry output is $C_{i+1} = G_i + P_i C_i$.

By recursively expanding $C_{i+1}$, we write all carry equations purely in terms of initial inputs $A_i, B_i$ and initial carry $C_0$:

C₁ = G₀ + P₀ C₀ Carry for Bit 1 (2 gate delays)

C₂ = G₁ + P₁ C₁ = G₁ + P₁ (G₀ + P₀ C₀) = G₁ + P₁ G₀ + P₁ P₀ C₀ Carry for Bit 2 (2 gate delays)

C₃ = G₂ + P₂ C₂ = G₂ + P₂ G₁ + P₂ P₁ G₀ + P₂ P₁ P₀ C₀ Carry for Bit 3 (2 gate delays)

C₄ = G₃ + P₃ C₃ = G₃ + P₃ G₂ + P₃ P₂ G₁ + P₃ P₂ P₁ G₀ + P₃ P₂ P₁ P₀ C₀ Carry for Bit 4 (2 gate delays)

Why CLA is Fast

Every carry $C_1, C_2, C_3, C_4$ is generated in **exactly 2 gate delays** (one AND layer for products, one OR layer for sum) regardless of bit width $N$. Thus, total addition time drops from $O(N)$ to $O(1)$ constant time (typically 4 gate delays total: 1 for $P_i/G_i$, 2 for Lookahead Carry Generator, 1 for final Sum XOR).

4.5 Multiplexers (MUX) Design

A Multiplexer (MUX), or "Data Selector", is a combinational circuit that selects binary information from one of $2^n$ input lines and directs it to a single output line based on $n$ select lines.

4.5.1 4-to-1 Multiplexer (4:1 MUX)

Contains 4 data inputs ($I_0, I_1, I_2, I_3$), 2 selection inputs ($S_1, S_0$), an Enable input ($\bar{E}$), and 1 output ($Y$).

Enable (Ē)	S₁	S₀	Selected Output (Y)
1	X	X	0 (Disabled)
0	0	0	I₀
0	0	1	I₁
0	1	0	I₂
0	1	1	I₃

Boolean Equation for 4:1 MUX:

Y = Ē · [ S̄₁ S̄₀ I₀ + S̄₁ S₀ I₁ + S₁ S̄₀ I₂ + S₁ S₀ I₃ ]

4.5.2 Implementing Arbitrary Boolean Functions using MUX

An $n$-variable Boolean function can be implemented using a $2^{n-1}$-to-1 MUX (with $n-1$ selection lines connected to $n-1$ variables, and the remaining variable connected to the data inputs).

Worked Example: Implement $F(A, B, C) = \sum m(1, 3, 5, 6)$ using a 4:1 MUX

1. Use variables $A$ and $B$ as select lines ($S_1 = A, S_0 = B$).
2. Variable $C$ will be applied to data lines $I_0, I_1, I_2, I_3$.
3. Construct the Implementation Table:

Input Line	I₀	I₁	I₂	I₃
C̄ (C=0)	m₀	m₁	m₄	m₆
C (C=1)	m₂	m₃	m₅	m⇁
Data Input Value	0	1	C	C̄

Conclusion: Connect $I_0 = 0$, $I_1 = 1$, $I_2 = C$, and $I_3 = \bar{C}$. Connect $A \to S_1$ and $B \to S_0$.

4.6 Demultiplexers (DEMUX) Design

A Demultiplexer (DEMUX), or "Data Distributor", takes a single input data line $D$ and routes it to one of $2^n$ possible output lines based on $n$ selection lines.

4.6.1 1-to-4 Demultiplexer (1:4 DEMUX)

Select Lines		Outputs
S₁	S₀	Y₀	Y₁	Y₂	Y₃
0	0	D	0	0	0
0	1	0	D	0	0
1	0	0	0	D	0
1	1	0	0	0	D

Logic Equations:

Y₀ = S̄₁ S̄₀ D , Y₁ = S̄₁ S₀ D , Y₂ = S₁ S̄₀ D , Y₃ = S₁ S₀ D

Decoder vs Demultiplexer Equivalence

A decoder with an Enable input line ($\bar{E}$ or $E$) functions identically to a Demultiplexer where the Enable signal is treated as Data Input $D$.

4.7 Basic Encoders

An Encoder performs the inverse operation of a decoder. It accepts $2^N$ (or fewer) input lines and compresses them into an $N$-bit binary output code.

4.7.1 Octal-to-Binary Encoder (8-to-3 Encoder)

Inputs (Only one active high at a time)								Outputs
D₀	D₁	D₂	D₃	D₄	D₅	D₆	D₇	Y₂	Y₁	Y₀
1	0	0	0	0	0	0	0	0	0	0
0	1	0	0	0	0	0	0	0	0	1
0	0	1	0	0	0	0	0	0	1	0
0	0	0	1	0	0	0	0	0	1	1
0	0	0	0	1	0	0	0	1	0	0
0	0	0	0	0	1	0	0	1	0	1
0	0	0	0	0	0	1	0	1	1	0
0	0	0	0	0	0	0	1	1	1	1

Derived Logic Equations:

$Y_2 = D_4 + D_5 + D_6 + D_7$
$Y_1 = D_2 + D_3 + D_6 + D_7$
$Y_0 = D_1 + D_3 + D_5 + D_7$

Severe Limitations of Basic Encoders

Multiple Active Inputs Malfunction: If $D_3$ and $D_6$ are both 1 simultaneously, output becomes $111_2 = 7_{10}$, which is completely invalid.
Ambiguity with Input $D_0$: When all inputs $D_0 \dots D_7$ are 0, output is $000$, making it indistinguishable from active $D_0 = 1$.

4.8 Priority Encoders

A Priority Encoder solves basic encoder defects by enforcing a strict priority hierarchy among inputs. If two or more inputs are active concurrently, the input with the highest priority index is encoded, and lower priority active inputs are ignored.

4.8.1 4-to-2 Priority Encoder ($D_3$ Highest Priority)

Inputs				Outputs
D₃	D₂	D₁	D₀	x (Y₁)	y (Y₀)	Valid Bit (V)
0	0	0	0	X	X	0
0	0	0	1	0	0	1
0	0	1	X	0	1	1
0	1	X	X	1	0	1
1	X	X	X	1	1	1

K-Map Derivation for Priority Encoder:

K-Map for x ($Y_1$)

x = D₂ + D₃

K-Map for y ($Y_0$)

y = D₃ + D₁ D̄₂

Valid Output Bit (V)

V = D₀ + D₁ + D₂ + D₃

4.9 Encoder Designs: Decimal-to-BCD Encoder

A Decimal-to-BCD Encoder (10-to-4 line encoder) converts 10 decimal digits ($0$ through $9$) represented on distinct push-buttons or keypad lines into a 4-bit Binary-Coded Decimal (BCD) number ($Y_3 Y_2 Y_1 Y_0$).

Decimal Input Key	Y₃ (8)	Y₂ (4)	Y₁ (2)	Y₀ (1)
D₀	0	0	0	0
D₁	0	0	0	1
D₂	0	0	1	0
D₃	0	0	1	1
D₄	0	1	0	0
D₅	0	1	0	1
D₆	0	1	1	0
D₇	0	1	1	1
D₈	1	0	0	0
D₉	1	0	0	1

Derived Logic Equations for OR-gate Array:

$Y_3$ (MSB): $D_8 + D_9$
$Y_2$: $D_4 + D_5 + D_6 + D_7$
$Y_1$: $D_2 + D_3 + D_6 + D_7$
$Y_0$ (LSB): $D_1 + D_3 + D_5 + D_7 + D_9$

4.10 Decoder Designs and Tree Expansion

A Decoder decodes an $N$-bit binary input into up to $2^N$ unique individual minterm output lines.

4.10.1 2-to-4 Line Decoder with Enable Line ($E$)

Enable (E)	A	B	Y₀ (m₀)	Y₁ (m₁)	Y₂ (m₂)	Y₃ (m₃)
0	X	X	0	0	0	0
1	0	0	1	0	0	0
1	0	1	0	1	0	0
1	1	0	0	0	1	0
1	1	1	0	0	0	1

4.10.2 Tree Expansion: Building a 3-to-8 Decoder using Two 2-to-4 Decoders

We use the most significant input bit ($A$) to enable either the upper or lower 2-to-4 decoders through an inverter:

3-to-8 Decoder Tree Architecture

                          ┌───────────────────────────┐
                          │     2-to-4 Decoder 1      │
                  ┌───────│ Enable (E = Ā)            │─── Y0..Y3 (m0..m3)
                  │       │ Inputs: B, C              │
Input A ───[NOT]──┴─┐     └───────────────────────────┘
                    │
                    │     ┌───────────────────────────┐
                    │     │     2-to-4 Decoder 2      │
                    └─────│ Enable (E = A)            │─── Y4..Y7 (m4..m7)
                          │ Inputs: B, C              │
                          └───────────────────────────┘

4.11 BCD-to-Decimal Decoder

A BCD-to-Decimal Decoder (7442 IC) converts a 4-bit BCD code ($A, B, C, D$) into one of 10 active-low or active-high decimal outputs ($Y_0 \dots Y_9$). Input combinations from $1010_2$ to $1111_2$ ($10$ to $15$) are invalid BCD states and are treated as Don't Cares ($X$).

BCD Inputs				Active-High Outputs
A (8)	B (4)	C (2)	D (1)	Y₀	Y₁	Y₂	Y₃	Y₄	Y₅	Y₆	Y₇	Y₈	Y₉
0	0	0	0	1	0	0	0	0	0	0	0	0	0
0	0	0	1	0	1	0	0	0	0	0	0	0	0
0	0	1	0	0	0	1	0	0	0	0	0	0	0
0	0	1	1	0	0	0	1	0	0	0	0	0	0
0	1	0	0	0	0	0	0	1	0	0	0	0	0
0	1	0	1	0	0	0	0	0	1	0	0	0	0
0	1	1	0	0	0	0	0	0	0	1	0	0	0
0	1	1	1	0	0	0	0	0	0	0	1	0	0
1	0	0	0	0	0	0	0	0	0	0	0	1	0
1	0	0	1	0	0	0	0	0	0	0	0	0	1

Simplified Logic Equations (taking advantage of Don't Cares $10-15$):

Y₀ = ĀB̄C̄D̄ , Y₁ = ĀB̄C̄D , Y₈ = A D̄ , Y₉ = A D

4.12 Seven-Segment Decoder

A Seven-Segment Decoder converts a 4-bit BCD input ($W, X, Y, Z$) into activation signals for 7 display LEDs labeled $a, b, c, d, e, f, g$.

Standard 7-Segment Digit Layout (Displaying Digit 0: Segments a-f ON, g OFF)

4.12.1 Common Cathode vs. Common Anode Configurations

Common Cathode (CC): All LED cathodes are tied to GND. A logic 1 (High) turns a segment ON.
Common Anode (CA): All LED anodes are tied to $V_{CC}$. A logic 0 (Low) turns a segment ON.

4.12.2 Truth Table for BCD to Seven-Segment Decoder (Common Cathode)

Digit	BCD Inputs (W X Y Z)				a	b	c	d	e	f	g
0	0	0	0	0	1	1	1	1	1	1	0
1	0	0	0	1	0	1	1	0	0	0	0
2	0	0	1	0	1	1	0	1	1	0	1
3	0	0	1	1	1	1	1	1	0	0	1
4	0	1	0	0	0	1	1	0	0	1	1
5	0	1	0	1	1	0	1	1	0	1	1
6	0	1	1	0	1	0	1	1	1	1	1
7	0	1	1	1	1	1	1	0	0	0	0
8	1	0	0	0	1	1	1	1	1	1	1
9	1	0	0	1	1	1	1	1	0	1	1

4.12.3 K-Map Simplification for Segment 'a'

K-Map for Segment a (Inputs W, X, Y, Z with Don't Cares for 10-15)

WX\YZ	00	01	11	10
00	1	0	1	1
01	0	1	1	1
11	X	X	X	X
10	1	1	X	X

Derived Minimal Equation for Segment 'a':

a = W + Y + X Z + X̄ Z̄

4.13 Magnitude Comparators

A Magnitude Comparator is a combinational circuit that compares two binary numbers $A$ and $B$ and determines their relative magnitudes, producing three output flags: $A > B$, $A = B$, and $A < B$.

4.13.1 1-Bit Magnitude Comparator

A	B	A > B	A = B	A < B
0	0	0	1	0
0	1	0	0	1
1	0	1	0	0
1	1	0	1	0

Equations: $(A > B) = A \bar{B} \quad, \quad (A < B) = \bar{A} B \quad, \quad (A = B) = A \odot B = \overline{A \oplus B}$.

4.13.2 4-Bit Magnitude Comparator (7485 IC Architecture)

To compare two 4-bit numbers $A = A_3 A_2 A_1 A_0$ and $B = B_3 B_2 B_1 B_0$, define bit-wise equality variables $x_i = A_i \odot B_i$ for $i \in \{0, 1, 2, 3\}$.

Full 4-Bit Comparison Equations:

(A = B) = x₃ · x₂ · x₁ · x₀ All bits must match exactly

(A > B) = A₃ B̄₃ + x₃ A₂ B̄₂ + x₃ x₂ A₁ B̄₁ + x₃ x₂ x₁ A₀ B̄₀ Cascade checking from MSB to LSB

(A < B) = Ā₃ B₃ + x₃ Ā₂ B₂ + x₃ x₂ Ā₁ B₁ + x₃ x₂ x₁ Ā₀ B₀ Cascade checking from MSB to LSB

Cascading Comparators for Larger Bit Widths (e.g. 8-Bit)

Commercial ICs like the 74LS85 feature cascading inputs ($I_{A>B}, I_{A

Digit	BCD Inputs (W X Y Z)				a	b	c	d	e	f	g
0	0	0	0	0	1	1	1	1	1	1	0
1	0	0	0	1	0	1	1	0	0	0	0
2	0	0	1	0	1	1	0	1	1	0	1
3	0	0	1	1	1	1	1	1	0	0	1
4	0	1	0	0	0	1	1	0	0	1	1
5	0	1	0	1	1	0	1	1	0	1	1
6	0	1	1	0	1	0	1	1	1	1	1
7	0	1	1	1	1	1	1	0	0	0	0
8	1	0	0	0	1	1	1	1	1	1	1
9	1	0	0	1	1	1	1	1	0	1	1

Digit	BCD Inputs (W X Y Z)				a	b	c	d	e	f	g
0	0	0	0	0	1	1	1	1	1	1	0
1	0	0	0	1	0	1	1	0	0	0	0
2	0	0	1	0	1	1	0	1	1	0	1
3	0	0	1	1	1	1	1	1	0	0	1
4	0	1	0	0	0	1	1	0	0	1	1
5	0	1	0	1	1	0	1	1	0	1	1
6	0	1	1	0	1	0	1	1	1	1	1
7	0	1	1	1	1	1	1	0	0	0	0
8	1	0	0	0	1	1	1	1	1	1	1
9	1	0	0	1	1	1	1	1	0	1	1

Digit	BCD Inputs (W X Y Z)				a	b	c	d	e	f	g
0	0	0	0	0	1	1	1	1	1	1	0
1	0	0	0	1	0	1	1	0	0	0	0
2	0	0	1	0	1	1	0	1	1	0	1
3	0	0	1	1	1	1	1	1	0	0	1
4	0	1	0	0	0	1	1	0	0	1	1
5	0	1	0	1	1	0	1	1	0	1	1
6	0	1	1	0	1	0	1	1	1	1	1
7	0	1	1	1	1	1	1	0	0	0	0
8	1	0	0	0	1	1	1	1	1	1	1
9	1	0	0	1	1	1	1	1	0	1	1