Digital Logic & Logic Gates

1. Foundations of Digital Logic & Signals

A Logic Gate is an idealized or physical electronic device implementing a Boolean function—a logical operation performed on one or more binary inputs that produces a single binary output.

1.1 Analog vs. Digital Signals

While analog signals vary continuously over a smooth range of voltages, digital logic operates within discrete voltage bands representing binary values:

• Logic 1 (HIGH / TRUE / ON): Represents the presence of a signal (typically $V_{CC}$ e.g., $+5\text{V}$ for TTL, $+3.3\text{V}$ or $+1.8\text{V}$ for modern CMOS).
• Logic 0 (LOW / FALSE / OFF): Represents the absence of a signal (typically ground / $0\text{V}$).

1.2 Positive Logic vs. Negative Logic Systems

The assignment of binary state values to physical voltage levels defines the logic polarity:

2. Basic Fundamental Gates

The foundation of all digital systems rests upon three elementary logical operations: NOT (Inversion), AND (Conjunction), and OR (Disjunction).

3. Universal Logic Gates

NAND and NOR gates are known as Universal Gates because any Boolean expression or logic function can be synthesized using only NAND or only NOR gates without requiring any other gate type.

4. Universal Gate Synthesis & Step-by-Step Proofs

This section proves universality by constructing all standard logic operations using solely 2-input NAND gates and solely 2-input NOR gates.

4.1 NAND Gate Realization Matrix

1. NOT from NAND (Requires 1 Gate): Connect both inputs together.

2. AND from NAND (Requires 2 Gates): Invert the output of a NAND gate using a second NAND-based inverter.

3. OR from NAND (Requires 3 Gates): Apply De Morgan's Law $A + B = (A' · B')'$. Invert inputs $A$ and $B$ individually via NAND inverters, then pass both into a 3rd NAND gate.

4. XOR from NAND (Requires 4 Gates): Realizing $Y = A\bar{B} + \bar{A}B$.

5. XNOR from NAND (Requires 5 Gates): Invert the output of the 4-gate NAND XOR circuit using a 5th NAND inverter.

4.2 NOR Gate Realization Matrix

1. NOT from NOR (Requires 1 Gate): Connect both inputs together.

2. OR from NOR (Requires 2 Gates): Invert the output of a NOR gate using a second NOR inverter.

3. AND from NOR (Requires 3 Gates): Apply De Morgan's Law $A · B = (A' + B')'$. Invert inputs $A$ and $B$ individually via NOR inverters, then pass into a 3rd NOR gate.

4. XNOR from NOR (Requires 4 Gates): Realizing $Y = AB + \bar{A}\bar{B}$.

5. XOR from NOR (Requires 5 Gates): Invert the output of the 4-gate NOR XNOR circuit using a 5th NOR inverter.

4.3 Universal Implementation Minimum Gate Count Summary

5. Exclusive & Special Purpose Gates

5.1 Practical Applications of XOR Gates

• Controlled Inverter / Programmable Complementer: If input $B$ is held at Logic 0, $Y = A \oplus 0 = A$ (Buffer). If input $B$ is held at Logic 1, $Y = A \oplus 1 = A'$ (Inverter).
• 1-Bit Half Adder: The Sum output $S = A \oplus B$, while Carry $C = A \cdot B$.
• Parity Generation & Checking: Cascaded XOR gates yield an output of 1 if the dataset contains an odd number of 1s.

6. Tri-State Logic & High-Impedance (High-Z)

Standard logic gates have two output states (0 and 1). Tri-State Logic adds a 3rd state called High-Impedance (High-Z), where the output is electrically disconnected from the circuit board trace.

7. Standard 7400 Series TTL IC Pinout Reference

Commercial Transistor-Transistor Logic (TTL) ICs come packaged in standard 14-pin Dual In-line Packages (DIP). Pin 7 is always connected to GND ($0\text{V}$) and Pin 14 is connected to $V_{CC}$ ($+5\text{V}$).

8. Key Electrical Parameters & Characteristics

8.1 Propagation Delay ($t_p$)

The transition time required for an output signal to change state after an input signal transition occurs:

• $t_{pLH}$ (Propagation Delay LOW to HIGH): Time interval between input trigger and output transition from 0 to 1.
• $t_{pHL}$ (Propagation Delay HIGH to LOW): Time interval between input trigger and output transition from 1 to 0.
• Average Delay: $t_p = \frac{t_{pLH} + t_{pHL}}{2}$ (Typical standard TTL: $10\text{ ns}$).

8.2 Fan-In and Fan-Out

• Fan-In: The maximum number of inputs a logic gate can physically process simultaneously.
• Fan-Out: The maximum number of standard logic gate inputs that a single logic gate output can reliably drive without voltage degradation outside allowable thresholds.

8.3 Noise Margins

Noise margin quantifies the electrical noise immunity of a logic family:

For standard 5V TTL logic: $V_{IH(min)} = 2.0\text{V}$, $V_{OH(min)} = 2.4\text{V}$, $V_{IL(max)} = 0.8\text{V}$, $V_{OL(max)} = 0.4\text{V}$. Yielding a safety noise margin $NM_H = NM_L = 0.4\text{V}$.

9. Master Logic Gate Cheatsheet