Chapter 6: Registers and Counters

Tribhuvan University (TU) - Institute of Engineering (IOE) | BCT 2nd Semester

Teaching Hours: 7 Hours

6.1 Register Fundamentals & Register Types

A register is a digital electronic device composed of a group of flip-flops driven by a common clock signal, designed to store and manipulate multi-bit binary data. A single flip-flop can store 1 bit of information. Therefore, an $N$-bit register consists of $N$ flip-flops capable of storing an $N$-bit binary word.

Basic Operational Characteristics

While basic memory cells hold data statically, registers typically incorporate combinational logic gates to enable operational control such as parallel loading, clear, hold, and bidirectional bit-shifting.

Storage Capacity of an $N$-bit Register = $N$ bits = $2^N$ distinct binary states ($00...0$ to $11...1$)

Classification of Registers

Storage (Buffer) Registers: Hold binary data without altering bit positions until overwritten or cleared (e.g., memory buffer registers).
Shift Registers: Possess the ability to move binary data left or right by one bit position per clock edge. Data shift direction depends on control inputs and inter-flip-flop wiring.
Universal Shift Registers: Capable of operating in multiple modes (Parallel Load, Shift Left, Shift Right, Hold) governed by mode-select control lines.

Key IOE Exam Concept: Storage registers accept data simultaneously on all inputs (Parallel Load). Shift registers transfer bits sequentially from one flip-flop to the next adjacent flip-flop upon each active clock pulse transition.

6.2 SISO, SIPO, PISO, and PIPO Registers

Shift registers are classified into four fundamental architectures based on how data is loaded into the register and how data is retrieved from it.

1. Serial-In, Serial-Out (SISO) Shift Register

In a SISO shift register, binary data is entered one bit at a time via a single input pin, and extracted one bit at a time from the output pin of the final stage. To shift an $N$-bit data word entirely through an $N$-bit SISO register, $N$ clock cycles are required to load, and $N$ clock cycles are required to read out (Total $2N - 1$ cycles for full sequence if continuous).

Figure 6.2a: 4-Bit Serial-In, Serial-Out (SISO) Shift Register Logic Diagram

2. Serial-In, Parallel-Out (SIPO) Shift Register

Data enters serially bit-by-bit just as in SISO. However, all flip-flop outputs ($Q_0, Q_1, Q_2, Q_3$) are tapped and made available simultaneously on parallel output lines. Conversion from serial communication to parallel data processing requires $N$ clock cycles for an $N$-bit word.

3. Parallel-In, Serial-Out (PISO) Shift Register

Parallel data bits ($D_0, D_1, D_2, D_3$) are loaded simultaneously into the flip-flops during a single clock cycle when the $\text{Shift}/\overline{\text{Load}}$ control signal is LOW. When $\text{Shift}/\overline{\text{Load}}$ is HIGH, the internal combinational logic connects the output of stage $n$ to the input of stage $n+1$, allowing the loaded data to be shifted out serially one bit per clock cycle.

Figure 6.2b: Functional Representation of PISO Shift Register with Load/Shift Gating

4. Parallel-In, Parallel-Out (PIPO) Shift Register

Data bits are loaded simultaneously from parallel input lines on an active clock pulse and retrieved immediately on parallel output lines. It operates as a high-speed buffer memory requiring only 1 clock cycle to store and present data.

Comparison Matrix of Register Architectures

Register Type	Loading Time (Clock Cycles)	Retrieval Time (Clock Cycles)	Primary Application
SISO	$N$	$N$	Signal Delay Line, Serial Memory Buffer
SIPO	$N$	$1$	Serial-to-Parallel Data Conversion (e.g., UART receiver)
PISO	$1$	$N$	Parallel-to-Serial Data Conversion (e.g., UART transmitter)
PIPO	$1$	$1$	High-Speed CPU Internal Registers, Data Latches

6.3 Data Transfer Timing Diagrams

Timing diagrams illustrate bit shifts across flip-flop stages on successive active clock edges. Consider shifting a 4-bit data stream $1011_2$ (MSB to LSB order: $D_3=1, D_2=0, D_1=1, D_0=1$) into a 4-bit SISO register initially cleared ($Q_3 Q_2 Q_1 Q_0 = 0000$).

Shift Sequence State Table

Clock Pulse (CP)	Serial Data In	$Q_3$ (MSB Stage)	$Q_2$	$Q_1$	$Q_0$ (LSB Stage)
Initial State	-	0	0	0	0
CP 1	1	1	0	0	0
CP 2	1	1	1	0	0
CP 3	0	0	1	1	0
CP 4	1	1	0	1	1

Waveform Timing Analysis

Figure 6.3: SISO Timing Diagram Showing Data Propagation Across Stages Q3, Q2, Q1

6.4 Asynchronous (Ripple) Counters

An asynchronous counter (commonly called a ripple counter) is a sequential logic circuit where the external clock pulse is directly applied only to the first (LSB) flip-flop stage. The output of each flip-flop stage serves as the trigger clock input for the subsequent flip-flop stage.

Operating Mechanism and Features

Flip-flops operate in toggle mode ($T=1$ or $J=K=1$).
Because clocking propagates like a ripple through a chain of flip-flops, individual stages do not toggle simultaneously.
Cumulative Propagation Delay: If each flip-flop has a propagation delay of $t_{pd}$, an $N$-stage asynchronous counter experiences a total delay of: $$\text{Total Delay } (T_{delay}) = N \times t_{pd}$$
Maximum Operating Frequency Limitation: To avoid counting errors, the input clock period $T_{clk}$ must satisfy: $$T_{clk} \ge N \times t_{pd} \implies f_{max} = \frac{1}{N \cdot t_{pd}}$$

Glitch Hazard / Spikes: Due to cumulative propagation delays, temporary invalid decoding states (glitches or decoding spikes) occur during transitions. For example, when transitioning from $011_2 \to 100_2$, intermediate states such as $010_2$ or $000_2$ exist for nanoseconds, which can trigger erroneous logic in external combinational circuits.

6.5 Up, Down, and Mod-N Asynchronous Counters

1. 3-Bit Asynchronous Up Counter

To construct a ripple counter that counts upwards ($0 \to 1 \to 2 \to \dots \to 2^N-1$), negative-edge-triggered flip-flops are connected such that the non-inverted output $Q_n$ of stage $n$ drives the clock input of stage $n+1$.

Figure 6.5a: 3-Bit Ripple Up Counter using Negative-Edge-Triggered JK Flip-Flops

Rules for Asynchronous Up/Down Clocking Configuration:

Up Counter: Use Negative Edge Trigger with $Q$ driving next CLK OR Positive Edge Trigger with $\overline{Q}$ driving next CLK.
Down Counter: Use Negative Edge Trigger with $\overline{Q}$ driving next CLK OR Positive Edge Trigger with $Q$ driving next CLK.

2. Mod-N Asynchronous Counter (Truncated Sequence)

A Modulo-$N$ (or Mod-$N$) counter resets to 0 after completing $N$ distinct count states ($0$ through $N-1$). To design a Mod-$N$ counter from a cascade of flip-flops capable of counting up to $2^k > N$, active-LOW asynchronous clear ($\overline{\text{CLR}}$) inputs are driven by a NAND gate that decodes state $N$.

Example Design: Asynchronous Mod-6 Counter

Count Sequence: $000_2 (0) \to 001_2 (1) \to 010_2 (2) \to 011_2 (3) \to 100_2 (4) \to 101_2 (5)$. Upon reaching state $6$ ($110_2$), the counter must immediately reset back to $000_2$.

Binary for state 6 ($N=6$): $Q_2 Q_1 Q_0 = 110_2$.
NAND Clear Gate Input: Connected to outputs $Q_2$ and $Q_1$.
Clear Equation: $\overline{\text{CLR}} = \overline{Q_2 \cdot Q_1}$.
When $Q_2=1$ and $Q_1=1$, $\overline{\text{CLR}} = 0$, instantly resetting all flip-flops to $000$. State 6 exists only momentarily as a narrow transient spike (glitch).

Figure 6.5b: Asynchronous Mod-6 Counter with Active-LOW Feedback Clear Logic

6.6 Synchronous Counters

In a synchronous counter, all flip-flops are connected to a single common clock signal. Consequently, all flip-flop state changes occur simultaneously at the exact instant of the active clock edge, entirely eliminating the cumulative propagation delays inherent in ripple counters.

Comparison: Asynchronous vs. Synchronous Counters

Parameter	Asynchronous (Ripple) Counter	Synchronous Counter
Clock Application	Applied only to LSB stage; subsequent stages clocked by prior FF outputs.	Applied simultaneously to all flip-flops.
Propagation Delay	Cumulative ($T_{delay} = N \cdot t_{pd}$). Increases linearly with bit count.	Constant ($T_{delay} = t_{pd} + t_{gate\_delay}$). Independent of bit length.
Maximum Speed	Low operating frequency for high bit widths.	Very high operating frequency capability.
Decoding Glitches	High probability due to intermediate transition delays.	Minimal/Absent; output transitions occur simultaneously.
Design Complexity	Simple wiring, minimal extra combinational logic.	Requires excitation tables, K-maps, and input logic gate arrays.

General Design Methodology for Synchronous Counters

Determine the required number of flip-flops $N$ such that $2^N \ge \text{Modulo Count}$.
Draw the complete State Transition Diagram and construct the State Table detailing Present States ($Q_n$) and Next States ($Q_{n+1}$).
Utilize the Excitation Table of the selected flip-flop (JK, T, or D) to determine required control inputs for every state transition.
Construct Karnaugh Maps (K-maps) for each flip-flop input variable to simplify logical expressions.
Implement the minimized combinational logic functions driving the flip-flop control inputs.

6.7 Up, Down, and Mod-N Synchronous Counters

Detailed Design Example: 3-Bit Synchronous Up Counter (using JK Flip-Flops)

Count Sequence: $000_2 \to 001_2 \to 010_2 \to 011_2 \to 100_2 \to 101_2 \to 110_2 \to 111_2 \to 000_2$.

Step 1 & 2: State Transition & Excitation Table

Recall JK Flip-Flop Excitation Requirements: $0\to 0: J=0, K=X$; $0\to 1: J=1, K=X$; $1\to 0: J=X, K=1$; $1\to 1: J=X, K=0$.

Present State			Next State			FF₂ Inputs		FF₁ Inputs		FF₀ Inputs
$Q_2$	$Q_1$	$Q_0$	$Q_2^+$	$Q_1^+$	$Q_0^+$	$J_2$	$K_2$	$J_1$	$K_1$	$J_0$	$K_0$
0	0	0	0	0	1	0	X	0	X	1	X
0	0	1	0	1	0	0	X	1	X	X	1
0	1	0	0	1	1	0	X	X	0	1	X
0	1	1	1	0	0	1	X	X	1	X	1
1	0	0	1	0	1	X	0	0	X	1	X
1	0	1	1	1	0	X	0	1	X	X	1
1	1	0	1	1	1	X	0	X	0	1	X
1	1	1	0	0	0	X	1	X	1	X	1

Step 3: K-Map Simplification

$$J_0 = 1, \quad K_0 = 1$$ $$J_1 = Q_0, \quad K_1 = Q_0$$ $$J_2 = Q_1 \cdot Q_0, \quad K_2 = Q_1 \cdot Q_0$$

Step 4: Schematic Circuit Diagram

Figure 6.7: 3-Bit Synchronous Up Counter Circuit Schema using Common Clock Line

Up/Down Synchronous Counter with Mode Control Lines

An Up/Down counter incorporates a control input $M$. When $M=1$, the counter increments; when $M=0$, it decrements.

Generalized Excitation Input for Stage $n$: $$J_n = K_n = (M \cdot Q_{n-1} \cdot \dots \cdot Q_0) + (\overline{M} \cdot \overline{Q_{n-1}} \cdot \dots \cdot \overline{Q_0})$$

Lockout Phenomenon and Self-Starting Counters

In Mod-$N$ synchronous counters where $N < 2^k$, there exist $2^k - N$ unused (unmapped) states. If noise or power-on transients force the counter into an unused state:

Lockout State: The counter gets trapped in an isolated cycle of unused states and fails to return to the valid counting sequence.
Self-Starting Design: An expertly designed counter guarantees that for every unused state, the next-state logic forces a transition back into a valid state within a finite number of clock cycles.

6.8 Register and Counter Applications

Shift registers and counters form essential operational building blocks in computer architectures, digital signal processing (DSP), and control units.

1. Specialized Shift Register Counters

A. Ring Counter

A circular shift register where the output of the final flip-flop stage ($Q_N$) is fed directly back into the input of the first stage ($D_0$).

Initial seed value required: $100...0_2$.
Number of valid states for an $N$-bit register = $N$.
No external decoding logic required to identify states (directly usable for multi-phase timing clock generation).

B. Johnson (Twisted-Ring) Counter

A modified ring counter where the inverted output of the last stage ($\overline{Q_N}$) is connected to the input of the first stage ($D_0$).

Number of valid states = $2N$ for an $N$-bit register.
Self-cleaning capability can be added with minimal gating. Requires simple 2-input AND gates to decode any individual state.

Metric / Property	Standard Ring Counter	Johnson (Twisted Ring) Counter
Feedback Connection	$D_0 = Q_{N-1}$	$D_0 = \overline{Q_{N-1}}$
Number of States (Modulus)	$N$	$2N$
Flip-Flop Utilization Efficiency	Low ($N / 2^N$)	Moderate ($2N / 2^N$)
Decoding Gates Needed	None (1-out-of-N decoded outputs)	$N$ two-input AND gates

2. Additional System Applications

Serial Adder Circuitry: Employs shift registers to serially feed binary operands into a single 1-bit full adder stage, saving hardware area in resource-constrained systems.
Pseudo-Random Binary Sequence (PRBS) Generators: Utilizes Linear Feedback Shift Registers (LFSRs) with XOR feedback taps to generate white noise and cryptographic keys.
Frequency Division: Mod-$N$ counters divide input clock frequencies by exactly $N$, essential for system clock generation and baud rate synthesis.
Digital Clocks & Timers: Cascaded Mod-10 (BCD) and Mod-6 counters format frequency-divided pulses into seconds, minutes, and hours.
Analog-to-Digital Conversion (ADC): Dual-slope and successive-approximation ADCs utilize binary counters to perform voltage-to-time digitization.

Present State			Next State			FF₂ Inputs		FF₁ Inputs		FF₀ Inputs
\(Q_2\)	\(Q_1\)	\(Q_0\)	\(Q_2^+\)	\(Q_1^+\)	\(Q_0^+\)	\(J_2\)	\(K_2\)	\(J_1\)	\(K_1\)	\(J_0\)	\(K_0\)
0	0	0	0	0	1	0	X	0	X	1	X
0	0	1	0	1	0	0	X	1	X	X	1
0	1	0	0	1	1	0	X	X	0	1	X
0	1	1	1	0	0	1	X	X	1	X	1
1	0	0	1	0	1	X	0	0	X	1	X
1	0	1	1	1	0	X	0	1	X	X	1
1	1	0	1	1	1	X	0	X	0	1	X
1	1	1	0	0	0	X	1	X	1	X	1

Register Type	Loading Time (Clock Cycles)	Retrieval Time (Clock Cycles)	Primary Application
SISO	\(N\)	\(N\)	Signal Delay Line, Serial Memory Buffer
SIPO	\(N\)	\(1\)	Serial-to-Parallel Data Conversion (e.g., UART receiver)
PISO	\(1\)	\(N\)	Parallel-to-Serial Data Conversion (e.g., UART transmitter)
PIPO	\(1\)	\(1\)	High-Speed CPU Internal Registers, Data Latches

Metric / Property	Standard Ring Counter	Johnson (Twisted Ring) Counter
Feedback Connection	\(D_0 = Q_{N-1}\)	\(D_0 = \overline{Q_{N-1}}\)
Number of States (Modulus)	\(N\)	\(2N\)
Flip-Flop Utilization Efficiency	Low (\(N / 2^N\))	Moderate (\(2N / 2^N\))
Decoding Gates Needed	None (1-out-of-N decoded outputs)	\(N\) two-input AND gates