Module 5: Sequential Logic Circuits

Comprehensive Academic Reference Guide for Computer Engineering (TU / IOE Syllabus)

5.1 Latches and Flip-Flops: SR, D, T, and JK

A Sequential Logic Circuit is a circuit whose present output depends not only on the present input combinations, but also on the past history of inputs (internal memory state). The memory element forms a feedback loop in the circuit.

Fundamental Distinction: Latch vs. Flip-Flop

Latch: An asynchronous, level-triggered storage element. It continuously samples inputs and updates outputs whenever the enable signal ($EN$) is active (High or Low).
Flip-Flop: A synchronous, edge-triggered storage element. It changes state only at specific clock transitions (Positive Rising Edge $\uparrow$ or Negative Falling Edge $\downarrow$).

5.1.1 SR Latch (Set-Reset)

The SR Latch can be built using cross-coupled NOR or NAND gates. It maintains a binary state until inputs signal a change.

NOR-Based Active-HIGH SR Latch

Cross-Coupled NOR SR Latch

R ────►[ NOR1 ]───────────► Q
          ▲         │
          │         ▼
          │      [ Feedback Cross-Coupling ]
          ▼         │
S ────►[ NOR2 ]─────┴─────► Q'

S	R	Q_n+1 (Next State)	Q'_n+1	Action / Operating Mode
0	0	Q_n	Q'_n	No Change (Hold State)
0	1	0	1	Reset State (Q cleared to 0)
1	0	1	0	Set State (Q set to 1)
1	1	0	0	Invalid / Forbidden State (Violates $Q = \overline{Q'}$)

NAND-Based Active-LOW S'R' Latch

Constructed with cross-coupled NAND gates. Operating modes are activated by driving inputs Low ($0$). Setting $\bar{S}=0, \bar{R}=0$ leads to the invalid state $Q = Q' = 1$.

5.1.2 Clocked / Gated D Latch (Data or Delay)

The D latch eliminates the invalid state of the SR latch by driving $S$ with $D$ and $R$ with $\bar{D}$ through an inverter. It transfers input $D$ directly to output $Q$ when Enable $EN=1$.

EN	D	Q_n+1	Operating Condition
0	X	Q_n	Disabled / Hold State
1	0	0	Reset State
1	1	1	Set State

5.1.3 JK Flip-Flop

The JK Flip-Flop resolves the forbidden condition of the SR flip-flop. When both $J=1$ and $K=1$, the flip-flop toggles its current output state ($Q_{n+1} = \bar{Q}_n$).

CLK	J	K	Q_n+1	State Description
0 or ↓	X	X	Q_n	No Change (Clock Inactive)
↑	0	0	Q_n	Hold / No Change
↑	0	1	0	Reset State
↑	1	0	1	Set State
↑	1	1	Q̄_n	Toggle State

5.1.4 T Flip-Flop (Toggle)

The T Flip-Flop is created by shorting inputs $J$ and $K$ together on a JK Flip-Flop ($J = K = T$). If $T=0$, state is held; if $T=1$, output toggles on every active clock edge.

CLK	T	Q_n+1	Functional Action
↑	0	Q_n	Hold / No Change
↑	1	Q̄_n	Toggle Output State

5.2 Excitation Tables and Characteristic Equations

Flip-flops are defined analytically by two representations:

Characteristic Table / Equation: Defines the Next State ($Q_{n+1}$) as a function of the Present State ($Q_n$) and Inputs.
Excitation Table: Defines the Required Inputs needed to force a state transition from Present State ($Q_n$) to Next State ($Q_{n+1}$). Used during circuit synthesis and conversions.

5.2.1 Characteristic Tables & Derivations

SR Flip-Flop

Q_n	S	R	Q_n+1
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	X
1	0	0	1
1	0	1	0
1	1	0	1
1	1	1	X

JK Flip-Flop

Q_n	J	K	Q_n+1
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	1
1	0	0	1
1	0	1	0
1	1	0	1
1	1	1	0

5.2.2 K-Map Simplification for Characteristic Equations

JK Flip-Flop Next State $Q_{n+1}$

Q_n\JK	00	01	11	10
0	0	0	1	1
1	1	0	0	1

Q_{n+1} = J Q̄_n + K̄ Q_n

T Flip-Flop Next State $Q_{n+1}$

Q_n\T	0	1
0	0	1
1	1	0

Q_{n+1} = T ⊕ Q_n = T Q̄_n + T̄ Q_n

Summary of All Flip-Flop Characteristic Equations

SR Flip-Flop: $Q_{n+1} = S + \bar{R}Q_n \quad \text{Constraint: } S \cdot R = 0$
D Flip-Flop: $Q_{n+1} = D$
JK Flip-Flop: $Q_{n+1} = J\bar{Q}_n + \bar{K}Q_n$
T Flip-Flop: $Q_{n+1} = T \oplus Q_n = T\bar{Q}_n + \bar{T}Q_n$

5.2.3 Master Excitation Matrix for All Flip-Flops

This table compares the required inputs for each flip-flop type to execute a given state transition ($Q_n \to Q_{n+1}$):

State Transition		SR Inputs		D Input	JK Inputs		T Input
Q_n	Q_n+1	S	R	D	J	K	T
0	0	0	X	0	0	X	0
0	1	1	0	1	1	X	1
1	0	0	1	0	X	1	1
1	1	X	0	1	X	0	0

5.3 Master-Slave Flip-Flops

5.3.1 The Race-Around Condition in Level-Triggered JK Flip-Flops

In a level-triggered JK flip-flop, if $J = 1$ and $K = 1$ while the clock pulse remains High ($CLK=1$) for a time duration $t_p$ that exceeds the propagation delay $\Delta t$ of the flip-flop logic gates ($t_p > \Delta t$):

1. Output Q changes from 0 to 1 after Δt Toggle condition J=1, K=1

2. Since CLK is still High, new state Q=1 feeds back to gates Feedback loop remains active

3. Output toggles again from 1 to 0 after another Δt Continuous oscillations during tp

4. Final output Q at clock edge becomes unstable & unpredictable Race-Around Condition

5.3.2 Master-Slave JK Flip-Flop Architecture

A Master-Slave Flip-Flop resolves the race-around condition by cascading two clocked SR/JK latches in series with complementary clock signals.

Master-Slave JK Flip-Flop Circuit Diagram

         ┌─────────────────────────┐               ┌─────────────────────────┐
J ──────►│  MASTER JK LATCH        │─── Y (Qm) ───►│  SLAVE SR LATCH         │──────► Q
         │ Active when CLK = 1     │               │ Active when CLK = 0     │
K ──────►│                         │─── Y' (Qm')──►│                         │──────► Q'
         └────────────┬────────────┘               └────────────┬────────────┘
                      │                                         │
CLK ──────────────────┴───────────────[ NOT ]───────────────────┘

Operation Mechanics:

When Clock $CLK = 1$: The Master latch is enabled ($CLK=1$), while the Slave latch is isolated ($CLK'=0$). The Master samples inputs $J$ and $K$ and sets its intermediate state $Y$. The main output $Q$ remains unchanged.
When Clock $CLK$ transitions from $1 \to 0$: The Master latch turns OFF, locking its output state $Y$. Simultaneously, the inverted clock turns the Slave latch ON. The Slave reads $Y$ and updates the main outputs $Q$ and $Q'$.

Because the main output $Q$ changes state only when the master input stage is disabled, feedback cannot re-enter the master stage during the same clock pulse, eliminating the race-around condition.

5.4 Flip-Flop Timing Diagrams

5.4.1 Critical Timing Parameters

Setup Time ($t_{su}$): The minimum duration of time that data inputs ($D, J, K, S, R$) must remain stable before the arrival of the active clock edge.
Hold Time ($t_h$): The minimum duration of time that data inputs must remain constant after the active clock edge.
Propagation Delay ($t_{pd}$): The time delay between the active clock edge trigger and the corresponding output state change at $Q$.

Timing Waveforms & Constraints

CLK    : ───────┐               ┌───────┐               ┌───────
                │               │       │               │
                └───────────────┘       └───────────────┘
                                ▲
                                │ Active Rising Edge
D      : ─────────────[ Valid Data ]─────────────────────────────
                      ◄── t_su ─►◄─ t_h ─►

Q      : ─────────────────────────┐──────────────────────────────
                                  │◄─ t_pd ─►
                                  └──────────────────────────────

5.5 Flip-Flops as Finite State Machines (FSMs)

Any sequential circuit containing flip-flops and combinational logic can be modeled as a Finite State Machine (FSM). The circuit moves through a discrete set of states based on clock cycles and external inputs.

5.5.1 Classification: Mealy vs. Moore FSM Models

Feature	Moore Machine	Mealy Machine
Output Dependence	Output depends only on Present State ($Y = f(Q_n)$)	Output depends on Present State AND Inputs ($Y = f(Q_n, X)$)
State Diagram Representation	Outputs are written inside state nodes (State / Output)	Outputs are written on transition arrows (Input / Output)
Hardware Complexity	Generally requires more states to implement a given function	Requires fewer states than a Moore machine
Response to Inputs	Outputs change synchronously with clock edge	Outputs can change asynchronously when inputs change

Structural Block Diagram of an FSM

              ┌───────────────────────────┐
Inputs (X) ──►│ Next State Logic          │──► Next State (Qn+1) ──►┌────────────┐
              │ (Combinational Circuit)   │                       │ State      │──► Present State (Qn)
              └─────────────┬─────────────┘                       │ Memory     │      │
                            ▲                                     │ Flip-Flops │      │
                            └─────────────────────────────────────└────────────┘      │
                                                                                      │
Outputs (Y) ◄───[ Output Logic Circuit ]◄──────────────────────────────────────────────┘
               (Also takes Inputs X in Mealy Model)

5.6 Flip-Flop Conversions

Any source flip-flop type can be converted into a target flip-flop type by connecting an appropriate combinational logic circuit to the inputs of the source flip-flop.

Standard Conversion Methodology

Identify the Target FF (desired behavior) and the Source FF (available component).
Construct a composite truth table listing: Target Inputs | Present State ($Q_n$) | Next State ($Q_{n+1}$) | Source Inputs.
Fill in $Q_{n+1}$ using the Target FF's characteristic behavior.
Use the Excitation Table of the Source FF to determine the required Source Inputs for every transition from $Q_n \to Q_{n+1}$.
Minimize expressions for the Source Inputs using K-Maps and draw the logic circuit.

5.6.1 Example 1: Convert SR Flip-Flop to JK Flip-Flop

Target: JK Flip-Flop | Source: SR Flip-Flop

Target Inputs		Present State	Next State	Source SR Inputs
J	K	Q_n	Q_n+1	S	R
0	0	0	0	0	X
0	0	1	1	X	0
0	1	0	0	0	X
0	1	1	0	0	1
1	0	0	1	1	0
1	0	1	1	X	0
1	1	0	1	1	0
1	1	1	0	0	1

K-Map Minimization for S and R Inputs:

K-Map for Input S

S = J Q̄_n

K-Map for Input R

R = K Q_n

Converted JK Flip-Flop Circuit

J ───[ AND1 ]──────► S ┌──────────┐
       ▲               │ SR FF    │───► Q
Q' ────┼───────────────┤          │
       │               └──────────┘
K ───[ AND2 ]──────► R │
       ▲               │
Q ─────┘               └──────────┘

5.6.2 Example 2: Convert JK Flip-Flop to D Flip-Flop

Target: D Flip-Flop | Source: JK Flip-Flop

Target D	Present Q_n	Next Q_n+1	Source J	Source K
0	0	0	0	X
0	1	0	X	1
1	0	1	1	X
1	1	1	X	0

Derived Equations: $J = D$ and $K = \bar{D}$. Connecting $D$ to $J$ and $\bar{D}$ to $K$ converts a JK FF into a D FF.

5.7 Flip-Flop Applications

5.7.1 Registers and Shift Registers

A register is a group of flip-flops used to store binary data. Shift registers move stored data bits laterally across stages on every clock pulse.

Serial-In, Serial-Out (SISO): Data is loaded and retrieved sequentially, bit-by-bit.
Serial-In, Parallel-Out (SIPO): Data enters serially and is read concurrently across all bit positions.
Parallel-In, Serial-Out (PISO): Bits are loaded simultaneously via control lines and shifted out bit-by-bit.
Parallel-In, Parallel-Out (PIPO): Data is loaded and retrieved simultaneously in a single clock cycle.

Specialized Shift Register Counters:

Ring Counter: An $N$-bit shift register with inverted output $Q_N$ connected back to input $D_1$. Requires initial seeding with $100\dots 0$. Total unique states = $N$.
Johnson Counter (Twisted Ring Counter): Output $Q_N'$ is fed back to $D_1$. Total unique states = $2N$. Eliminates self-starting issues.

5.7.2 Synchronous and Asynchronous Binary Counters

Asynchronous (Ripple) Counters

The output $Q$ of stage $i$ serves as the clock input for stage $i+1$. Flip-flops switch sequentially, causing accumulated ripple propagation delays.

Synchronous Counters

All flip-flops receive the clock signal simultaneously. Next states are determined concurrently using combinational logic, eliminating ripple delays.

5.7.3 Frequency Division Circuits

A single T Flip-Flop configured with $T=1$ (or D FF with $Q'$ connected back to $D$) toggles state every clock pulse, producing an output square wave with exactly half the clock frequency ($f_{out} = f_{clk} / 2$). Cascading $N$ stages divides clock frequency by $2^N$.

5.7.4 Mechanical Switch Debouncing Circuit

Mechanical switches create contact bounce noises when toggled. An SR Latch filters out voltage spikes during contact bouncing, ensuring clean digital transition pulses.