Digital Logic – Chapters

1. Introduction, codes & number systems (7 marks)

1.1 Digital vs analog

Analog signals vary continuously; digital signals have discrete levels (0/1). Merits of digital: easier design, noise immunity, accurate storage, easy IC integration, error detection/correction, programmable, lower power. Demerits: needs A/D and D/A conversion, needs more bandwidth, real world is analog.

1.2 Logic levels, ICs, clock

Positive logic: HIGH=1, LOW=0. TTL: LOW 0–0.8 V, HIGH 2–5 V. ICs by size: SSI (<12 gates), MSI (12–99), LSI (100–9999), VLSI (10⁴+), ULSI. Clock triggering: level (high/low) or edge (positive/negative). Flip-flops use edge triggering. Applications: computers, communication, control, instrumentation, consumer electronics.

1.3 Number systems

Decimal→binary: repeated ÷2 (integer), ×2 (fraction). Binary↔octal: groups of 3 bits; binary↔hex: groups of 4 bits.

(6E.2C)₁₆ → octal: 0110 1110.0010 1100 → 01 101 110 . 001 011 000 = 156.130₈

1.4 Codes

BCD: each decimal digit as 4 bits. BCD addition: if a nibble sum >9 or carry occurs, add 0110.

23+48 in BCD: 0010 0011 + 0100 1000 = 0110 1011; low nibble >9, add 0110 → 0111 0001 = 71

Excess-3: BCD + 0011 (self-complementing).

159 → 0001 0101 1001 + 0011 each → 0100 1000 1100

Gray: only one bit changes between successive codes. Binary→Gray: MSB same, then g_i=b_i⊕b_i−1. Gray→binary: MSB same, then b_i=b_i−1⊕g_i.

10011→11101; 110001→100001; 10110110→11011011; binary 101101→Gray 111011

1.5 Alphanumeric codes

ASCII: 7-bit (128 characters; 'A'=65=1000001, 'a'=97, '0'=48), 8-bit extended. EBCDIC: IBM 8-bit code, 256 characters, used in mainframes.

1.6 Complements & signed numbers

1's complement: invert bits. 2's complement: 1's complement + 1. Signed magnitude: MSB=sign. Range of n-bit 2's complement: −2ⁿ⁻¹ to +2ⁿ⁻¹−1. Subtraction A−B = A + 2's complement of B; carry out is discarded when the result is positive; overflow when two operands of the same sign give a different sign.

(−28)+12, 8-bit: +28=00011100 → −28=11100100; +12=00001100; sum=11110000 = −16

2. Logic gates (4 marks)

Basic: AND (AB), OR (A+B), NOT (A'). Universal: NAND, NOR. Exclusive: XOR (A⊕B=A'B+AB', odd number of 1s), XNOR (A⊙B=AB+A'B', equality).

Universal gates

NAND: NOT = (A·A)'; AND = ((AB)')' i.e. NAND followed by NAND-as-NOT; OR = (A'·B')' = A+B using inverted inputs. NOR: NOT = (A+A)'; OR = ((A+B)')'; AND = (A'+B')' = AB. Because NOT, AND and OR can be built from either gate alone, both are universal.

XOR from 4 NANDs: X=(AB)', Y=(A·X)', Z=(B·X)', out=(YZ)'.

De Morgan's laws

(A+B)' = A'·B' and (AB)' = A'+B'. Truth table proof: for AB=00,01,10,11 both (AB)' and A'+B' give 1,1,1,0; (A+B)' and A'B' give 1,0,0,0. NAND = bubbled OR; NOR = bubbled AND.

Positive/negative logic

Positive logic: HIGH=1. Negative logic: LOW=1. A positive AND gate acts as a negative OR gate, and NAND↔NOR.

3. Boolean algebra & K-maps (5 marks)

Laws: A+0=A, A·1=A, A+1=1, A·0=0, A+A=A, A+A'=1, A·A'=0, (A')'=A; commutative, associative, distributive (A+BC=(A+B)(A+C)); absorption A+AB=A; A+A'B=A+B; consensus AB+A'C+BC=AB+A'C; duality.

Prove AB+A'C+BC=AB+A'C: BC=BC(A+A')=ABC+A'BC. Then AB+ABC=AB and A'C+A'BC=A'C. ∎
Prove AB+C(A⊕B)=BC+A(B+C): expand both sides in minterms; LHS=AB+A'BC+AB'C, RHS=BC+AB+AC=AB+BC+AC, which has the same minterms 3,5,6,7. ∎

Minterm: product of all variables (m); maxterm: sum of all variables (M). SOP=ΣM minterms; POS=ΠM maxterms. K-map uses Gray order (00,01,11,10). Groups of 1, 2 (pairs), 4 (quads), 8 (octets); groups may roll over edges and corners (rolling), overlapping is allowed, don't-cares (X) are used only if they enlarge a group. Redundant groups are ones whose cells are all covered by other groups.

F=Σm(1,2,4,5,6,8,10,11,13,15): one minimal form = A'C'D + AB'D' + A'BD' + B'CD' + ACD + BC'D (realize with AND-OR or NAND-NAND).

Steps: truth table → K-map → group largest first, essential prime implicants first → write SOP → draw gates.

4. Combinational circuits (10 marks)

Design steps: problem → inputs/outputs → truth table → K-map → simplified equations → logic diagram.

Circuit	Equations
Half adder	S=A⊕B, C=AB
Full adder	S=A⊕B⊕Cin, Cout=AB+Cin(A⊕B)
Half subtractor	D=A⊕B, Bo=A'B
Full subtractor	D=A⊕B⊕Bin, Bo=A'B+(A⊕B)'Bin

Ripple-carry adder: n full adders chained; carry ripples, so delay grows with n. Fast (look-ahead): G=AB, P=A⊕B, C_i+1=G_i+P_iC_i computed in parallel.

Multiplexer (MUX) & demultiplexer

MUX: 2ⁿ inputs, n selects, 1 output; Y=Σ m_iD_i. A 4:1 MUX: Y=S1'S0'D0+S1'S0D1+S1S0'D2+S1S0D3. Larger MUX from smaller ones (MUX tree; 16:1 = four 4:1 + one 4:1). DEMUX: one input routed to one of 2ⁿ outputs (1:4: Y0=D·S1'S0' …); acts as decoder if D=1.

Full adder using 4:1 MUX (selects A,B): Sum inputs for AB=00,01,10,11 = Cin, Cin', Cin', Cin; Carry inputs = 0, Cin, Cin, 1.
Full subtractor using 4:1 MUX (selects A,B): Difference inputs = Bin, Bin', Bin', Bin; Borrow inputs = Bin, 1, 0, Bin.
Half+full adder in one circuit, Y=Σm(0,2,3,5,7) with 1:4 MUX: use the same method, with select lines as two variables and data inputs from the third (0,1,X,X').

Encoders & decoders

Encoder: 2ⁿ inputs → n-bit code. Octal-to-binary: A2=D4+D5+D6+D7, A1=D2+D3+D6+D7, A0=D1+D3+D5+D7 (OR gates). Priority encoder outputs code of the highest-priority active input (X=don't care for lower ones) and a valid bit V. 16-to-4 line uses 15 lines' OR gates (each output OR of 8 inputs). Decimal-to-BCD: A=D8+D9, B=D4+D5+D6+D7, C=D2+D3+D6+D7, D=D1+D3+D5+D7+D9.

Decoder: n inputs → 2ⁿ outputs (each output one minterm). 3×8 decoder + OR gates realizes any function of 3 variables (OR the required minterm outputs; use NAND if outputs are active low). 4×16 from two 3×8 with enable, or 5 of 2×4. BCD-to-decimal: 4→10 decoder, outputs Y0–Y9, invalid codes 1010–1111 give none.

Seven-segment decoder (common cathode: 1 lights)

Segment f is ON for 0,4,5,6,8,9; don't cares 10–15 → f = A + BC' + BD' + C'D'. Draw each segment by K-map similarly.

Magnitude comparator

1-bit: A>B=AB', A=B=A⊙B, A<B=A'B. n-bit: compare MSB first; equality x_i=A_i⊙B_i. For 3-bit: (A=B)=x2x1x0; (A>B)=A2B2'+x2A1B1'+x2x1A0B0'; (A<B)=A2'B2+x2A1'B1+x2x1A0'B0.

5. Sequential logic & flip-flops (7 marks)

Combinational vs sequential: combinational output depends only on present inputs (no memory, no clock); sequential also depends on past state (has memory, uses feedback and clock). Latch vs flip-flop: a latch is level-sensitive (transparent while enable is active); a flip-flop is edge-triggered and changes state only at the clock edge. Race-around in JK (J=K=1, level clock) is removed by master-slave or edge triggering.

FF	Characteristic eq.	Excitation (Q→Q⁺)
SR	Q⁺=S+R'Q (SR=0)	0→0: S=0,R=X; 0→1: 1,0; 1→0: 0,1; 1→1: X,0
JK	Q⁺=JQ'+K'Q	0→0: 0,X; 0→1: 1,X; 1→0: X,1; 1→1: X,0
D	Q⁺=D	D=Q⁺
T	Q⁺=T⊕Q	T=Q⊕Q⁺

SR: 00 hold, 01 reset, 10 set, 11 invalid. JK: 00 hold, 01 reset, 10 set, 11 toggle. Master-slave: master follows input while clock HIGH, slave copies at clock falling edge.

Conversions

Method: write the required FF's characteristic table, then the given FF's excitation table, and derive its inputs by K-map. SR→JK: S=JQ', R=KQ. D→JK: D=JQ'+K'Q. JK→T: J=K=T. JK→D: J=D, K=D'. SR→D: S=D, R=D'. SR→T: S=TQ', R=TQ. D→T: D=T⊕Q. To make a D flip-flop function as JK, feed D=JQ'+K'Q (AND/OR/NOT logic in front). Applications: registers, counters, frequency dividers, switch debouncing, data storage, state machines.

6. Registers & counters (10 marks)

Registers

A register is a group of flip-flops storing n bits. Types: SISO, SIPO, PISO, PIPO (serial/parallel in and out). A 4-bit shift register uses 4 D flip-flops with common clock; data moves one position per clock. Serial-in loading takes 4 clocks; SISO output after 4 more.

4-bit SIPO, input 1011 (LSB… first bit first): Q0 (first FF) starts 0000. After clocks the FFs hold 1000→? Shifting in bits 1,0,1,1 in that order gives Q3Q2Q1Q0 = 0001→0010→0101→1011. Parallel outputs read after 4 clocks; timing diagram shows each Q delayed by one clock.
PISO (1101): a SHIFT/LOAD line: LOAD=1 with clock loads 1101 via AND-OR gates; SHIFT then outputs 1,0,1,1 serially in 4 clocks.

Johnson (twisted-ring) counter: Q̄ of last FF fed back to first; 4 FFs → 8 states (0000,1000,1100,1110,1111,0111,0011,0001), mod 2n. Ring counter: Q of last to first; n states (one hot).

Asynchronous (ripple) counters

Flip-flop outputs clock the next FF (JK with J=K=1 or T). Simple, but delay accumulates. Up counter with negative-edge FFs: clock next FF from Q; down counter: from Q'. n FFs → mod 2ⁿ; frequency divided by 2ⁿ. Mod-N: use n such that 2ⁿ≥N and a NAND on FFs' outputs at count N to clear all (CLR active low).

BCD/decade (mod-10): 4 JK FFs, J=K=1, ripple clock; NAND of Q3 and Q1 (1010) → CLR of all FFs, giving 0000–1001.
Mod-12: 4 FFs, NAND of Q3 and Q2 (1100) resets.
Mod-6: 3 FFs, NAND of Q2, Q1 (110) resets.
3-bit up/down: clock of next FF = Q (up) or Q' (down), selected by an up/down control using AND-OR gates.

Synchronous counters

Common clock, all FFs change together; no ripple delay. Design steps: state diagram → state table → excitation table → K-map for each input → circuit + timing.

Counter (T FF)	Inputs
3-bit up	T0=1, T1=Q0, T2=Q1Q0
2-bit up/down (M=1 up)	T0=1, T1=M·Q0+M'·Q0'
Mod-10 (BCD) up	T0=1, T1=Q3'Q0, T2=Q1Q0, T3=Q2Q1Q0+Q3Q0

Mod-6 with T FFs (states 000→101→000): T0=1 except from state 101→000 (T0=1), T1: toggles when Q0=1 and Q2=0 → T1=Q2'Q0; T2: toggles at 011→100 and 101→000 → T2=Q1Q0+Q2Q0 (states 110,111 are don't cares). Draw the state diagram, table and timing (count 0–5 then reset).
For SR/JK versions use the same table with the SR/JK excitation table.

Applications: frequency division, digital clocks, event counting, timers, memory address, sequencing.

7. Sequential machine design (10 marks)

Design steps (always write all): 1) state diagram (Moore/Mealy) 2) state table 3) remove redundant states 4) state assignment (S0=00, S1=01, S2=10) 5) transition table 6) excitation table for chosen FF 7) K-maps for FF inputs and output 8) circuit diagram (+timing). Mealy: output depends on state and input; Moore: on state only. Redundant states: two states with the same next states and outputs merge.

Example: detect 011 (Mealy, overlapping), T flip-flops.
S0: initial/none; S1: last bit 0; S2: last bits 01.
S0: X=0→S1 (Z=0), X=1→S0 (0). S1: 0→S1 (0), 1→S2 (0). S2: 0→S1 (0), 1→S0 (Z=1).
Assignment S0=00, S1=01, S2=10, 11 unused (don't care). Using T=Q⊕Q⁺: T1 = Q1 + Q0X, T0 = Q0⊙X (XNOR), Z = Q1X.

Other sequences (110, 010, 101): same steps. 110: S0 (none), S1 (1), S2 (11); Z=1 when in S2 and X=0. 010: S0, S1 (0), S2 (01); Z=1 when S2 and X=0. 101: S0, S1 (1), S2 (10); Z=1 when S2 and X=1. With SR: S=Q⁺·Q', R=Q⁺'·Q (0→1: S=1,R=0; 1→0: S=0,R=1; hold: S=0/X,R=X/0). With D: D=Q⁺. With JK: use JK excitation table.

8. Digital ICs (7 marks)

BJT/MOSFET as switch: BJT: cutoff (OFF), saturation (ON, V_CE(sat)≈0.2 V). NMOS ON when V_GS>V_T; PMOS ON when V_GS<−|V_T|.

Logic-family characteristics (asked as a 4-mark answer)

Parameter	TTL	CMOS
Supply	5 V ±5%	3–18 V
V_IH(min)/V_IL(max)	2 V/0.8 V	0.7/0.3 V_DD
V_OH(min)/V_OL(max)	2.4 V/0.4 V	≈V_DD/≈0
Noise margin	0.4 V	≈30–45% of V_DD
Propagation delay	≈10 ns	≈50–100 ns (older)
Power/gate	≈10 mW	≈nW static
Fan-out	≈10	≈50

Others: speed–power product, noise immunity, packing density (CMOS higher), static sensitivity (CMOS needs care).

TTL NAND: multi-emitter input transistor Q1, phase splitter Q2, totem-pole output (Q3, Q4, diode). Any input LOW → Q1 conducts, Q2 off, Q4 on → output HIGH. All inputs HIGH → Q2 and Q3 on, output LOW. TTL NOT/NOR: single-emitter input; NOR uses parallel phase-splitter transistors so either input HIGH gives LOW.

CMOS NAND (2 inputs): 2 PMOS in parallel from V_DD to output, 2 NMOS in series to ground. Only A=B=1 turns both NMOS on and both PMOS off → Y=0; otherwise a PMOS conducts → Y=1. CMOS NOR: PMOS in series, NMOS in parallel. NOT: one PMOS + one NMOS.

Three-state (tri-state) TTL: outputs HIGH, LOW, or high-impedance (Hi-Z) when disabled; allows many devices on one bus.

Applications

Multiplexed display: several 7-segment digits share segment lines (one decoder); a counter and digit-select decoder enable one digit at a time at high speed, so persistence of vision shows all digits and reduces components/current.
Frequency counter: input → Schmitt trigger → AND gate with a precise gate pulse (time base from crystal oscillator + divider, e.g., 1 s). Counter counts pulses while gate is open; the latch/decoder/display shows the count = frequency; control logic resets before the next gate.
Time measurement: the unknown interval opens the gate; a known-frequency clock pulses (f) pass through and are counted (N). Time T = N/f. Counter cleared before each measurement, result latched and displayed.

Exam checklist

Draw neat diagrams and timing diagrams for every counter, register and machine.
Show the state table, excitation table, K-maps and equations for all design questions.
Practise the past-paper questions in the Home page list until you can do them within the time.