Marks map (60 marks)
| Ch | Topic | Marks | Priority |
|---|---|---|---|
| 1 | Introduction & codes | 7 | Gray, excess-3, BCD add, 2's comp |
| 2–3 | Gates, Boolean, K-map | 9 | Universal gates, De Morgan, 4-var K-map |
| 4 | Combinational | 10 | Adder/subtractor via MUX, encoder, decoder, 7-seg |
| 5 | Flip-flops | 7 | Conversions, latch vs FF |
| 6 | Registers/counters | 10 | SIPO/PISO, async & sync counters |
| 7 | Sequential machines | 10 | Sequence detector (always asked) |
| 8 | Digital ICs | 7 | TTL/CMOS NAND/NOR, applications |
Repeated in the past papers (do these first)
- Sequence detector (10 marks): 011, 110, 010, 101 with T / SR / D flip-flops. Every paper.
- Synchronous counter design (mod-6, mod-10, 2-bit up/down) with T, SR, JK.
- Asynchronous counter (BCD/mod-10, mod-12, 3-bit up/down, 3-bit ripple).
- Shift registers: SIPO/PISO with timing diagram; Johnson counter.
- K-map 4 variables (with don't cares) + logic diagram; decoder/MUX realization.
- Full adder / subtractor using MUX; octal encoder; magnitude comparator.
- Codes: Gray↔binary, excess-3, 2's complement, BCD addition, hex→octal.
- Short notes: TTL/CMOS characteristics, CMOS NAND/TTL NOR, frequency counter, time measurement, digital vs analog.
- Flip-flop modification: SR→JK, D→JK, latch vs flip-flop.
How to score 80%+
- All 12 questions are compulsory, so no chapter can be skipped.
- Design questions are the main marks (counters, machine, K-map ≈ 35). Learn the steps in order and show the table, equations, circuit and timing diagram.
- Draw neat labelled diagrams; state assumptions.
- Practise each solved example, then change the numbers.