Digital Logic (ENEX/EX 152) – BCT Model Answers
Tribhuvan University · IOE · BE (BEI, BCT) · Year I / Part II · 4 past papers solved independently
Each paper is answered as a stand-alone exam script: full working, truth/state tables, K-maps, circuit diagrams and timing diagrams. Repeated topics (SIPO, sequence detectors, ripple counters, MUX design…) are written out in full every time so every paper can be read on its own.
Paper 1 – 2083 Baishakh (Back)
Gray code · excess-3 · universal gates · K-map · encoder · MUX full subtractor · D→JK · SIPO · async BCD counter · sync mod-10 (T) · 011 detector (T) · logic familiesPaper 2 – 2082 Bhadra (Regular)
Binary→Gray · 2's complement & BCD add · De Morgan · K-map with don't cares · 3-bit comparator · MUX full adder · SR→JK · shift registers & Johnson counter · ripple counter · sync mod-6 (SR) · 110 detector (SR) · frequency counterPaper 3 – 2082 Baishakh (Back)
ASCII & signed addition · Boolean proofs · priority encoder · 3×8 decoder realization · up/down counter (T) · PISO · mod-12 async counter · 010 detector (D) · CMOS NAND & TTL · time measurementPaper 4 – 2081 Ashwin (Regular, 2080 batch)
Digital vs analog · hex→octal, Gray→binary · BCD-to-7-segment (f) · 4:1 MUX · half adder/subtractor · mod-6 down counter (JK) · SIPO · up/down async counter · 101 detector (SR) · TTL NOR & CMOS · frequency measurementMost repeated topics across the 4 papers
| Topic | Papers |
|---|---|
| Sequence detector (Mealy, overlapping) | 1, 2, 3, 4 |
| Synchronous counter design | 1, 2, 3, 4 |
| Asynchronous / ripple counter with timing diagram | 1, 2, 3, 4 |
| Shift register (SIPO/PISO) with timing diagram | 1, 2, 3, 4 |
| K-map minimisation + realization | 1, 2, 3, 4 |
| MUX / decoder / encoder implementation | 1, 2, 3, 4 |
| Logic families (TTL / CMOS) | 1, 3, 4 |
| Frequency / time measurement | 2, 3, 4 |
Exam tips
- Always state the assumption (Mealy, overlapping, MSB first, active-high…).
- Draw the state diagram → state table → excitation table → K-maps → equations → circuit, in that order.
- Label timing diagrams with the clock edge used.