Digital Logic (EX 152) – Model Answers · Paper 4

Tribhuvan University, IOE · BE (BEI, BCT) · Year I / Part II · Regular (New Course – 2080 Batch) · 2081 Ashwin · Full Marks 60 · Pass 24 · 3 hrs

1. Merits and demerits of digital signal over analog signal [2]

Merits of digital signals	Demerits of digital signals
Immune to noise; signal can be regenerated without loss	Needs A/D and D/C conversion for real-world (analog) signals
Easy to store, copy and process (memory, computers)	Quantization error; information lost between sample instants
Accuracy can be increased by adding bits	Needs larger bandwidth for the same information
Error detection/correction and encryption are possible	Sampling/conversion circuits add cost and delay
ICs are cheap, small, low power and easily reproducible	Cannot represent a continuous signal exactly

2. Conversions [2×1.5]

(a) (6E.2C)₁₆ = (?)₈

Hex → binary (4 bits per digit): 6 = 0110, E = 1110, 2 = 0010, C = 1100 → 0110 1110 . 0010 1100.
Regroup in 3 bits: integer part (from the point to the left) 01 101 110 → 001 101 110 = 1 5 6; fraction part (from the point to the right) 001 011 00 → 001 011 000 = 1 3 0.

(6E.2C)₁₆ = (156.13)₈ (check: 6E = 110 = 156₈; 0.2C = 44/256 = 0.171875 = 0.13₈)

(b) (10110110)_Gray = (?)₂

(10110110)_Gray = (11011011)₂

3. Simplest logic circuit for segment 'f' of BCD-to-seven-segment decoder [4]

Inputs: BCD digit ABCD (A = MSB). Segment f (upper-left bar) is ON for the digits 0, 4, 5, 6, 8, 9. Codes 10–15 never occur → don't care (X).

Fig: seven-segment display (a–g); segment f is the upper-left bar.

Octet A: m8,9,10,11,12,13,14,15 (using X) → A
Quad m0,4,12,8 (column CD = 00) → C'D'
Quad m4,5,12,13 → BC'
Quad m4,6,12,14 → BD'

f = A + BC' + BD' + C'D'

Fig: logic circuit for segment f (NOT gates for C', D'; three 2-input ANDs; one 4-input OR).

4. Y(A,B,C) = Σm(0,2,3,5,7) with a single 4:1 MUX; combined half adder / half subtractor [4+3]

(i) Y using a 4:1 MUX

Use A and B as select lines (S1 = A, S0 = B); the data inputs are functions of C.

Fig: Y = Σm(0,2,3,5,7) with one 4:1 MUX; C' from a NOT gate; I1 tied to logic 1.

(ii) Half adder and half subtractor in one circuit

Half adder: Sum = A⊕B, Carry = AB. Half subtractor: Diff = A⊕B, Borrow = A'B. Sum and Diff are identical. Introduce a mode input M (M = 0 → adder, M = 1 → subtractor):

S/D = A ⊕ B , C/Bo = (A ⊕ M)·B

For M = 0: A⊕0 = A → carry = AB. For M = 1: A⊕1 = A' → borrow = A'B.

Fig: combined half adder/subtractor – two XOR gates and one AND gate.

5. Synchronous mod-6 down counter using JK flip-flops [7]

Sequence (Q_CQ_BQ_A): 101 → 100 → 011 → 010 → 001 → 000 → 101 (5 down to 0, then back to 5). States 110, 111 unused (don't care). JK excitation: 0→0 (0,X); 0→1 (1,X); 1→0 (X,1); 1→1 (X,0).

K-maps (variables C, B, A):

J_B = CA'

K_B = A'

J_C = B'A'

K_C = A'

For FF-A: J_A = 1 in all even states and K_A = 1 in all odd states, the rest being don't care → J_A = K_A = 1 (toggles every clock).

J_A = K_A = 1; J_B = CA', K_B = A'; J_C = B'A', K_C = A'

Fig: mod-6 synchronous down counter; NOT gate gives A' (used by all gates); common clock for all JK flip-flops.

Fig: timing diagram (positive-edge clock, count 5→4→3→2→1→0→5). The unused states 110 and 111 lead to valid states (110→001, 111→110→001), so the counter is self-correcting.

6. 4-bit SIPO shift register – input data 1011 [3+7]

Working: four D flip-flops (A, B, C, D) are connected in cascade (Q_A→D_B, Q_B→D_C, Q_C→D_D) with a common clock. Serial data is applied to D_A, one bit per clock pulse (MSB first: 1,0,1,1). On every positive clock edge each FF takes the value of the FF on its left, so data moves one position to the right. After four clock pulses the four bits are present simultaneously at the parallel outputs Q_AQ_BQ_CQ_D – serial-to-parallel conversion. All FFs are cleared before the first pulse.

Fig: 4-bit SIPO shift register (parallel outputs Q_A, Q_B, Q_C, Q_D).

After the 4th pulse: Q_DQ_CQ_BQ_A = 1011 – the first bit entered is at Q_D, the last at Q_A.

Fig: timing diagram for input 1011 (outputs change at the rising clock edge).

7. 3-bit up/down asynchronous counter, negative-edge triggered clock [3+3]

Principle: three JK (or T) flip-flops in toggle mode (J = K = 1) with negative-edge triggering. FF-A (LSB) receives the external clock. A flip-flop toggles when the previous stage output makes a 1 → 0 transition. Therefore:

Up counting: clock of the next FF is taken from Q of the previous FF (falling edge of Q = 1→0 carry).
Down counting: clock of the next FF is taken from Q' of the previous FF.

A control input M (M = 1 → up, M = 0 → down) selects the source using AND–OR gates: CLK_B = M·Q_A + M'·Q_A', CLK_C = M·Q_B + M'·Q_B'.

Fig: 3-bit up/down ripple counter (FF clock inputs shown for the up mode, i.e. from Q; the two gate networks above select Q or Q' with M).

Fig: timing diagram – UP counting (M = 1): 000 → 111 → 000. Each output changes at the falling edge of the clock/previous output.

Fig: timing diagram – DOWN counting (M = 0): 000 → 111 → 110 → … → 000 (borrow from the 000 state sets the counter to 111).

8. Sequence detector for 101 using SR flip-flops (output Y = 1) [10]

Assumptions: Mealy machine with input X and output Y (called Z in the question), overlapping allowed (10101 gives two detections).

Step 1 – State diagram

S0: no progress. S1: last bit is 1. S2: last two bits are 10.

Fig: state diagram, edge label = X/Y. From S2, X = 1 completes 101 (Y = 1) and this last 1 starts a new sequence → S1.

Step 2 – State table (S0 = 00, S1 = 01, S2 = 10; A = MSB; 11 unused) with SR excitation

SR excitation: 0→0 (0,X); 0→1 (1,0); 1→0 (0,1); 1→1 (X,0).

Step 3 – K-maps (variables A, B, X)

S_A = BX'

R_A = A

S_B = X

R_B = BX'

Y = AX

S_A = BX', R_A = A, S_B = X, R_B = BX', Y = AX

Check: S_AR_A = BX'A = 0 (state 11 unused) and S_BR_B = XBX' = 0 → the forbidden S=R=1 never occurs.

Step 4 – Circuit

Fig: 101 detector using two SR flip-flops (common clock); S_B = X is connected directly; Y = AX from one AND gate.

Verification: input 1 0 1 from S0: X=1 → S1 (01); X=0 → S_A = BX' = 1, R_B = 1 → 10 (S2); X=1 → Y = AX = 1, R_A = 1, S_B = 1 → 01 (S1). ✓

9. Two-input TTL NOR gate; characteristics of CMOS family [5+2]

Fig: simplified 2-input TTL NOR gate. Q1A, Q1B: input transistors (inputs A, B); Q2A, Q2B: phase-splitter transistors connected in parallel (common collector and common emitter); Q3–D–Q4: totem-pole output; R1–R4: resistors; V_CC = +5 V.

Operation

A = B = 0: both input transistors conduct and take the base current away from Q2A, Q2B → both OFF. Q4 gets no base current (through R3 → 0) → OFF; Q3 is driven ON through R2 → output = V_CC − V_BE − V_D ≈ 3.4 V = logic 1.
A = 1, B = 0 (or A = 0, B = 1): the transistor with input 1 (say Q1A) is reverse-biased, so its collector current drives Q2A ON. Q2A (a parallel path) supplies the base of Q4 and lowers the base of Q3 → Q4 saturates, Q3 is OFF → output ≈ 0.2 V = logic 0.
A = B = 1: both Q2 transistors ON → Q4 ON, Q3 OFF → output = 0.

Because the Q2 transistors are in parallel, one input at 1 is enough to make the output 0: Y = (A + B)' (NOR).

Characteristics of CMOS family

Built from complementary n-MOS and p-MOS transistors; very low static power (≈ nW–µW), power rises with frequency (P ∝ C·V²·f).
Wide supply range (3–15 V for 4000B, 2–6 V for 74HC); logic levels ≈ 0 V and V_DD.
Very high noise margin (≈ 30–45 % of V_DD) and rail-to-rail output swing.
Very high input impedance → very large fan-out (> 50 gates, limited by capacitance).
Propagation delay ≈ 8–10 ns (HC), slower in the 4000 series; high packing density; needs protection against static discharge; unused inputs must not be left floating.

10. Frequency measurement – functional diagram and operation [4]

The frequency of a periodic signal is the number of cycles per second. A digital frequency meter counts the input cycles N during an accurately known gate time T: f = N / T.

Unknown signal f_x→Schmitt trigger
(pulse shaper)→AND (gate)→Decade counters→Latch→BCD-to-7-segment decoder → Display

Crystal oscillator (e.g. 1 MHz)→Decade dividers→Gate control FF (T-FF) – gate time 1 s / 0.1 s / 10 ms→ gate signal to AND; strobe to latch; then reset to counters

Operation: (1) The input is squared by the Schmitt trigger, giving one clean pulse per cycle. (2) The crystal oscillator is divided down by decade dividers to obtain a stable pulse of, say, 1 s, which a flip-flop turns into the gate signal (T = 1 s). (3) While the gate is high, the AND gate passes the input pulses and the counter counts them. (4) When the gate goes low the counting stops, the count N is transferred to the latch (strobe pulse) and displayed; then a reset pulse clears the counter for the next measurement. (5) Example: N = 3250 pulses in T = 1 s → f = 3.25 kHz; with T = 0.1 s the count 325 represents 3.25 kHz (decimal point shifted). Accuracy is decided by the crystal stability and the ±1 count error, so longer gate times give higher resolution.