Digital Logic (EX 152) – Model Answers · Paper 3

1. ASCII code; (−28 + 12)₁₀ in 8-bit 2's complement [1+3]

ASCII (American Standard Code for Information Interchange) is a 7-bit alphanumeric code that represents 128 characters (letters, digits, punctuation, control codes) – e.g. 'A' = 1000001 (65), 'a' = 1100001 (97), '0' = 0110000 (48). An 8th bit is often added as a parity bit.

(−28) + (+12) in 8-bit signed representation

+28        = 0001 1100
1's compl. = 1110 0011
+ 1        = 1110 0100   ← −28 in 2's complement
+12        = 0000 1100

  1110 0100   (−28)
+ 0000 1100   (+12)
-------------
  1111 0000   (no carry out of MSB)

MSB = 1 → the result is negative and is in 2's complement form. Magnitude: 1's complement of 11110000 = 00001111, +1 = 00010000 = 16.

2. Prove the following [2×2]

(a) AB + A'C + BC = AB + A'C (consensus theorem)

LHS = AB + A'C + BC(A + A')   [since A + A' = 1]
= AB + A'C + ABC + A'BC
= AB(1 + C) + A'C(1 + B)
= AB + A'C = RHS ∎

(b) AB + C(A⊕B) = BC + A(B + C)

LHS = AB + C(AB' + A'B) = AB + AB'C + A'BC.
Write AB = ABC + ABC' :
LHS = ABC + ABC' + AB'C + A'BC = Σm(7, 6, 5, 3).
RHS = BC + AB + AC. Expanding each term into minterms: BC = ABC + A'BC (7,3); AB = ABC + ABC' (7,6); AC = ABC + AB'C (7,5). RHS = Σm(3,5,6,7).
LHS = RHS (both are the majority function) ∎

Truth-table verification of (b)

3. Decoder; octal priority encoder [2+6]

Decoder: a combinational circuit that converts an n-bit binary code on its inputs into 2ⁿ outputs, exactly one of which is active for each input combination (e.g. 3:8 decoder, built with AND/NAND gates and an enable input).

Octal priority encoder (8:3)

If more than one input is high, the input with the highest priority (D7 highest) is encoded. An extra output V (valid) shows that at least one input is active (needed to distinguish D0 from "no input").

From the table (X = don't care):

Fig: gate-level realization of the octal priority encoder (NOT gates generate D6', D5', D4', D2' etc.).

Fig: block diagram of the priority encoder.

4. Realize X(A,B,C,D) = Σm(0,2,3,7,8,10,11,14,15) using a single 3×8 decoder; simplify by K-map [3+3]

(i) Realization with one 3×8 decoder

A 3×8 decoder has only three select inputs, so the inputs A, B, C (A = MSB) are applied to the decoder and the fourth variable D is used with external gates. For each ABC combination (pair of minterms m_2k, m_2k+1):

(y_i = decoder output for ABC = i.) So: OR gate for y1, y5, y7 with two AND gates y3·D and (y0+y4)·D' and one final OR.

Fig: 3×8 decoder (A, B, C) with AND–OR gates and an inverter for D'. Terms shown: y1, y5, y7, y3·D, y0·D', y4·D' summed by OR gate.

(ii) K-map simplification

• Quad m0,2,8,10 (corners) → B'D'
• Quad m3,7,11,15 → CD
• Quad m10,11,14,15 → AC

The quad m2,3,10,11 (B'C) is redundant – all its cells are already covered.

Fig: minimized AND–OR realization.

5. Synchronous 2-bit up/down counter using T flip-flops [7]

Let M be the mode input: M = 1 → up count, M = 0 → down count. State = Q_BQ_A. Up: 00→01→10→11→00. Down: 00→11→10→01→00. For a T FF, T = Q ⊕ Q+.

K-maps (variables M, Q_B, Q_A):

Fig: 2-bit up/down counter – T_A tied to logic 1; T_B from an XNOR (= AND–OR) network of M and Q_A; common clock.

6. 4-bit PISO shift register – data 1101 [3+2]

Operation: the register has a control input SH/LD'. Each D input is fed through a 2:1 multiplexer (AND–OR gates) selecting between the parallel input P_i (SH/LD' = 0, load mode) and the output of the previous FF (SH/LD' = 1, shift mode). With SH/LD' = 0 a clock pulse loads all four bits (1101) in parallel. With SH/LD' = 1 each following clock pulse shifts the data one place towards the output FF-D; the bits appear one after the other at the serial output Q_D. Serial input of FF-A is tied to 0, so zeros fill in from the left.

Fig: 4-bit PISO register (M = 2:1 multiplexer: 0 → P_i, 1 → previous Q; select = SH/LD').

Fig: timing diagram for parallel data 1101 (P_AP_BP_CP_D = 1,1,0,1). First clock (LD mode) loads the data; the next four clocks shift it out. Serial output stream Q_D = 1, 0, 1, 1 (LSB first).

In the timing diagram the first period (before the load edge) is the initial cleared state.

7. Mod-12 asynchronous counter (positive edge, JK flip-flops) with timing diagram [3+3]

Circuit: four JK flip-flops (J = K = 1) are positive-edge triggered; clock of each following FF is taken from Q' of the preceding FF (up count). Mod-12 means count 0000 (0) to 1011 (11); at the 12th pulse the count would become 1100. The first state in which Q3 = Q2 = 1 is 1100, so a NAND gate with inputs Q3 and Q2 is connected to the active-low CLEAR inputs of all FFs: it clears the counter to 0000 immediately (reset at 12 → sequence 0…11).

Fig: mod-12 asynchronous counter; NAND(Q3,Q2) → CLR.

Fig: timing diagram (ideal). Q0 = f/2, Q1 = f/4, Q2 = f/8; Q3 is high during counts 8–11; the state 1100 lasts only for a few ns (reset glitch). Output of Q3 has period 12 T_clk (frequency f/12).

8. Sequence detector for 010 using D flip-flops (output Y = 1 on detection) [10]

Assumptions: Mealy machine, overlapping sequences allowed (…01010 gives two detections). Input X, output Y.

Step 1 – State diagram

S0: initial / no match (last bit 1 or reset). S1: last bit = 0. S2: last two bits = 01.

Fig: state diagram, edge label = X/Y. From S2 with X = 0 the sequence 010 is complete (Y = 1) and the final 0 is the start of a new sequence → S1.

Step 2 – State table and code assignment (S0 = 00, S1 = 01, S2 = 10; A = MSB; 11 unused)

For a D flip-flop, D = next state (D_A = A+, D_B = B+).

Step 3 – K-maps (variables A, B, X)

Step 4 – Circuit

Fig: 010 detector using two D flip-flops (common clock) – one AND gate for D_A, one NOT gate for D_B and one AND gate (with X') for Y.

Verification: input 0 1 0 starting from S0: X=0 → 01 (S1); X=1 → 10 (S2); X=0 → Y = A·X' = 1 and next state 01. ✓

9. Two-input CMOS NAND gate; characteristics of TTL family [4+2]

Fig: 2-input CMOS NAND – two PMOS in parallel (pull-up) between V_DD and Y, two NMOS in series (pull-down) between Y and ground. Inputs A, B connect to both a PMOS and an NMOS gate.

Logic operation

• A = B = 0: both PMOS ON, both NMOS OFF → Y connected to V_DD → 1.
• A = 0, B = 1 (or A = 1, B = 0): one PMOS is ON (parallel path), the series NMOS path is broken → Y = 1.
• A = B = 1: both PMOS OFF, both NMOS ON in series → Y pulled to ground → 0.

Thus Y = (A·B)'. In every steady state only one network conducts, so static power is almost zero.

Characteristics of TTL family

• Built from bipolar transistors (multi-emitter input transistor and totem-pole output); supply V_CC = +5 V (±5 %).
• Logic levels: V_IL(max) = 0.8 V, V_IH(min) = 2 V, V_OL(max) = 0.4 V, V_OH(min) = 2.4 V; noise margin ≈ 0.4 V.
• Propagation delay ≈ 10 ns (standard TTL); power dissipation ≈ 10 mW per gate.
• Fan-out ≈ 10; totem-pole output gives good drive and fast switching; open-collector and tri-state versions exist.
• Unused inputs float to logic 1; good speed, but higher power than CMOS.

10. Time-measuring circuit – functional diagram and operation [4]

A digital time-interval meter measures the time between a START pulse and a STOP pulse by counting the number of pulses of a precise clock that occur in between: T = N × T_clk (T_clk = 1/f_clk).

Operation: (1) Before measurement the counter and control FF are reset. (2) The START pulse sets the control FF; its output enables the AND gate. (3) Clock pulses from the crystal oscillator pass through the AND gate and are counted by the decade counters. (4) The STOP pulse resets the FF, the AND gate closes and counting stops. (5) The count N is latched, decoded and shown on the seven-segment display. Example: with f_clk = 1 MHz (T_clk = 1 µs) and N = 2500, the interval T = 2500 µs = 2.5 ms. Resolution = one clock period; accuracy depends on oscillator stability (±1 count error).