Digital Logic (ENEX 152) – Model Answers · Paper 2

1. Convert binary codes to Gray codes [2+2]

Rule: MSB of Gray = MSB of binary; every other Gray bit = (binary bit) ⊕ (the binary bit to its left).

(a) (101101)₂

(b) (110001)₂

2. 2's complement representation; BCD addition 23 + 48 [1+2]

2's complement: a signed-number representation in which a positive number is written in ordinary binary (MSB = 0) and a negative number is written as the 2's complement of its magnitude (MSB = 1). 2's complement = 1's complement (invert all bits) + 1. Example (8-bit): +5 = 00000101; 1's complement = 11111010; add 1 → −5 = 11111011. It has only one zero and addition/subtraction use the same adder.

BCD addition 23 + 48

   23 = 0010 0011
 + 48 = 0100 1000
 ------------------
 Binary sum  0110 1011
 Low nibble 1011 (= 11 > 9) → invalid, add correction 0110
   1011 + 0110 = 1 0001  → digit 0001, carry 1 to upper nibble
 Upper nibble: 0110 + 1 = 0111 (valid, ≤ 9)
 Result = 0111 0001

3. De Morgan's theorems with truth table and diagrams [4]

Theorem 1: The complement of a product equals the sum of the complements: (A·B)' = A' + B'.
Theorem 2: The complement of a sum equals the product of the complements: (A + B)' = A'·B'.
They extend to any number of variables: (ABC…)' = A'+B'+C'+… and (A+B+C+…)' = A'B'C'….

Columns (AB)' and A'+B' are identical, and (A+B)' and A'B' are identical, so both theorems are proved.

Fig 1: NAND gate ≡ OR gate with inverted inputs (bubbled OR): (AB)' = A'+B'

Fig 2: NOR gate ≡ AND gate with inverted inputs (bubbled AND): (A+B)' = A'B'

4. Minimize F(A,B,C,D) = Σm(0,1,2,4,7,8,9,10,12,15) + d(5,11,13) [5]

• Octet (all cells of columns CD = 00 and 01, using don't cares 5 and 13): m0,1,4,5,8,9,12,13 → C'
• Quad (four corners, wrap-around): m0,2,8,10 → B'D'
• Quad (using don't cares 5, 13): m5,7,13,15 → BD

Don't care 11 is not used (left as 0). Every 1-cell (0,1,2,4,7,8,9,10,12,15) is covered.

Fig: (left) AND–OR realization with NOT gates; (right) equivalent realization using an XNOR gate and an OR gate: F = C' + (B⊙D).

5. Magnitude comparator; 3-bit magnitude comparator [1+5]

Magnitude comparator: a combinational circuit that compares two binary numbers A and B and gives three outputs: A > B, A = B, A < B (only one is 1 at a time).

Design of 3-bit comparator (A = A2A1A0, B = B2B1B0)

1-bit comparison (A_i vs B_i): A>B = A_iB_i', A<B = A_i'B_i, A=B = A_i⊙B_i = A_iB_i + A_i'B_i'. Define equality of each bit x_i = A_i ⊙ B_i.

Comparison starts from the MSB: if the MSBs differ, the result is decided; if equal, compare the next bit, and so on.

Fig: 3-bit comparator – x_i are three XNOR gates (A_i, B_i); A>B and A<B from AND–OR networks; A=B from a 3-input AND.

6. Full adder using multiplexer [4]

S = A⊕B⊕Cin, Cout = AB + BCin + ACin. Use two 4:1 MUX with S1 = A, S0 = B.

Fig: full adder using two 4:1 multiplexers and one inverter (for Cin').

7. Combinational vs sequential circuit; convert SR flip-flop into JK flip-flop [2+5]

SR → JK conversion

Step 1: Excitation table of SR FF: Q→Q+ : 0→0 (S=0, R=X); 0→1 (S=1, R=0); 1→0 (S=0, R=1); 1→1 (S=X, R=0).

Step 2: Conversion table (JK = external inputs, Q_n = present state):

Step 3: K-maps for S and R (variables J, K, Q)

Step 4: Circuit – two AND gates in front of the SR FF, with Q' fed to the J gate and Q fed to the K gate. Since S·R = JQ'KQ = 0, the forbidden state never occurs (J=K=1 toggles).

Fig: S = J·Q', R = K·Q applied to the S and R inputs of an SR flip-flop (clocked); outputs Q, Q'.

8. Types of shift registers; Johnson counter [2+3]

A shift register is a group of flip-flops connected in cascade that stores binary data and shifts it left or right on each clock pulse. Types (by data entry/exit):

• SISO – serial in, serial out: delay line / data storage.
• SIPO – serial in, parallel out: serial-to-parallel conversion.
• PISO – parallel in, serial out: parallel-to-serial conversion (needs Load/Shift control).
• PIPO – parallel in, parallel out: temporary storage.
• Bidirectional (shift left/right) and Universal register (parallel load + both shifts).

Johnson (twisted-ring) counter

A Johnson counter is a shift register whose inverted output Q' of the last flip-flop is fed back to the input D of the first flip-flop. An n-bit Johnson counter has 2n states (mod-2n); a 4-bit one is mod-8. Starting from 0000, 1s are shifted in from the left until the register is full (1111), then 0s are shifted in until 0000 again.

Fig: 4-bit Johnson counter (D flip-flops, common clock, Q'_D → D_A).

Fig: timing diagram – each output is a square wave of frequency f/8 shifted by one clock period from the previous one. Only 2-input gates are needed to decode any state (e.g. 0000 = A'D', 1000 = AB', 1111 = AD, 0111 = A'B).

9. 3-bit ripple up counter with positive-edge triggered clock [5]

Circuit: three JK flip-flops with J = K = 1 (toggle FFs). The external clock drives FF-A (LSB) only. Because the FFs are positive-edge triggered, the clock of each following FF is taken from the Q' output of the previous FF: a falling edge of Q (= rising edge of Q') then toggles the next FF, which gives up-counting. Q'_A → CLK of FF-B, Q'_B → CLK of FF-C. The FFs do not change simultaneously – the change ripples through (asynchronous counter).

Fig: 3-bit asynchronous up counter (J = K = 1).

Fig: timing diagram (ideal, propagation delay of each FF ignored). Q_A toggles at every rising clock edge (f/2), Q_B at every falling edge of Q_A (f/4), Q_C at every falling edge of Q_B (f/8).

Points: mod-8 counter, counts 000→111 then recycles to 000 (divide-by-8); total delay = 3 × t_pd, which limits the maximum clock frequency.

10. Synchronous mod-6 counter using SR flip-flops, with timing diagram [7]

Count sequence: 000→001→010→011→100→101→000 (Q_CQ_BQ_A); states 110, 111 unused (don't care). SR excitation: 0→0 (0,X); 0→1 (1,0); 1→0 (0,1); 1→1 (X,0).

K-maps (variables C, B, A):

(S=R=1 for FF-C occurs only in the unused state 111; to make the counter self-starting S_C = C'BA may be used instead.)

Fig: mod-6 synchronous counter (all FFs on a common clock).

Fig: timing diagram – Q_A has f/2; Q_C is high for counts 4 and 5; the whole cycle repeats every 6 clock pulses (output frequency = f/6).

11. Sequence detector for 110 using SR flip-flops [7]

Assumptions: Mealy machine, overlapping sequences allowed. Z = 1 when the last three inputs are 1,1,0.

Step 1 – State diagram

S0: no progress. S1: last bit is 1. S2: last two bits are 11.

Fig: state diagram (label = X/Z).

Step 2 – State table (S0 = 00, S1 = 01, S2 = 10; A = MSB; 11 unused)

Step 3 – K-maps (variables A, B, X)

Check: S_AR_A = BXX' = 0 and S_BR_B = 0, so the SR restriction is satisfied.

Step 4 – Circuit

Fig: 110 detector with two SR flip-flops (X = serial input, Z = output).

12. Short note on frequency counter [3]

A frequency counter measures the frequency of an unknown periodic signal by counting the number of its cycles in a precisely known time interval (gate time T): f = N / T.

Operation: the Schmitt trigger converts the input into clean pulses. The stable crystal time base is divided down to give a gate pulse of exactly T (e.g. 1 s). While the gate is open, the AND gate passes the pulses to the counter. When the gate closes, the count N is transferred to a latch, displayed, and the counter is reset for the next measurement. Example: N = 4500 in T = 1 s → f = 4.5 kHz; with T = 10 ms the display would show the frequency in units of 100 Hz. Accuracy depends on the crystal stability and on ±1 count error.