Digital Logic (ENEX 152) – Model Answers · Paper 1

1. Convert Gray codes to binary [2+2]

Rule: MSB of binary = MSB of Gray. Every next binary bit = (previous binary bit) ⊕ (present Gray bit).

(a) (10011)_Gray

(b) (110001)_Gray

2. Analog vs digital signal; 159 → excess-3 [1+2]

Excess-3 code: add 3 to each decimal digit, then write the 4-bit binary of the result.

3. NAND and NOR are universal gates [3]

A gate is universal if NOT, AND and OR (a complete set) can be built from it alone.

NAND as universal gate

• NOT: (A·A)' = A'
• AND: ((A·B)')' = A·B (NAND followed by NAND used as NOT)
• OR: (A'·B')' = A + B (De Morgan)

NOR as universal gate

• NOT: (A+A)' = A'
• OR: ((A+B)')' = A+B
• AND: (A'+B')' = A·B (De Morgan)

Hence any Boolean function can be realized with NAND gates only or NOR gates only. ∎

4. Minimize F(A,B,C,D) = Σm(1,2,4,5,6,8,10,11,13,15) using K-map and realize [5]

The map has no group of 4 or more (checked all quads), so only pairs are possible. Pairs used:

• m1,m5 → A'C'D (m1 is covered only by this pair → essential)
• m8,m10 → AB'D' (wrap-around; essential)
• m11,m15 → ACD
• m5,m13 → BC'D
• m4,m6 → A'BD' (wrap-around)
• m2,m6 → A'CD'

Cover check: 1,5 | 8,10 | 11,15 | 5,13 | 4,6 | 2,6 → all ten minterms covered. (m4 has no partner left except m5/m6, so at least 6 terms are needed.)

Realization (AND–OR, 6 three-input AND gates, one 6-input OR gate, 4 NOT gates for A', C', B', D'):

Fig: two-level AND–OR realization of F (can equally be built with NAND gates only).

5. Encoder vs decoder; octal-to-binary encoder [2+4]

Octal-to-binary (8:3) encoder

Eight inputs D0–D7 (only one high at a time), three outputs Y2 Y1 Y0.

From the table: Y2 = D4+D5+D6+D7, Y1 = D2+D3+D6+D7, Y0 = D1+D3+D5+D7 (D0 needs no gate; all outputs 0 for D0).

Fig: octal-to-binary encoder – three 4-input OR gates.

6. Full subtractor using multiplexer [4]

Inputs A (minuend), B (subtrahend), Bin (borrow in). D = A⊕B⊕Bin, Bout = A'B + A'Bin + B·Bin.

Use two 4:1 MUX with select lines S1 = A, S0 = B; the data inputs are read off the table for each AB pair (function of Bin):

Fig: full subtractor with two 4:1 MUX and one NOT gate (Bin' generated by an inverter).

7. Latch vs flip-flop; convert D flip-flop into JK flip-flop [2+5]

D flip-flop → JK flip-flop

Step 1: D FF: Q_n+1 = D, so the required D = Q_n+1. Step 2: conversion table (JK is the new input, D is the FF input to be found).

Step 3: K-map for D (variables J, K, Q).

Step 4: circuit – two AND gates and one OR gate in front of the D flip-flop, with Q and Q' fed back.

Fig: JK flip-flop built from a D flip-flop (D input generated by the logic on the left).

8. 4-bit SIPO shift register – data 1010 [5]

Working: four D flip-flops (A, B, C, D) share one clock. Serial data enters FF-A; on every clock edge each FF copies the output of the FF before it (Q_A→D_B, Q_B→D_C, Q_C→D_D). After 4 clock pulses all 4 bits are available together at Q_AQ_BQ_CQ_D (parallel output). Data is applied MSB first (1,0,1,0) at positive-edge clock; initially all FFs are cleared.

Fig: 4-bit SIPO shift register. Parallel outputs Q_A, Q_B, Q_C, Q_D.

After the 4th pulse Q_DQ_CQ_BQ_A = 1010 (the first bit entered has travelled to FF-D).

Fig: timing diagram (outputs change at the rising clock edge).

9. Asynchronous BCD (decade) counter [5]

Principle: a 4-bit ripple (asynchronous) counter counts 0000 to 1111. To make it a decade counter it is forced to clear as soon as it tries to reach 1010 (decimal 10). Four JK flip-flops are used with J = K = 1 (toggle mode), negative-edge triggered. The external clock drives FF-Q0; the output of each FF clocks the next one.

A 2-input NAND gate takes Q3 and Q1 (the first state in which both are 1 is 1010) and its output is connected to the active-low asynchronous CLEAR of all FFs. When the count reaches 1010 the NAND output goes low, all FFs are cleared instantly to 0000 and the count restarts. State 1010 exists only for a few nanoseconds (a glitch).

Fig: FF chain, J=K=1, clock of each FF taken from Q of the previous FF; NAND(Q3,Q1) → CLR of all four FFs.

Fig: timing diagram of the decade counter (count 0 to 9, then reset). Q0 toggles on every falling clock edge, Q1 on the falling edge of Q0, Q2 on that of Q1, Q3 on that of Q2. At the 10th falling edge Q3Q1 = 11 → reset → 0000.

The counter divides the clock frequency by 10 (mod-10).

* 1010 appears momentarily and is cleared immediately.

10. Synchronous mod-10 up counter using T flip-flops, with timing diagram [7]

Step 1 – State and excitation table. Four T flip-flops (Q3Q2Q1Q0) count 0000→1001→0000; states 1010–1111 are unused (don't care). For a T FF: T = Q_n ⊕ Q_n+1 (T = 1 when the bit must change).

Step 2 – K-maps (unused states 10–15 = X).

Step 3 – Logic diagram. All flip-flops receive the same clock.

Fig: mod-10 synchronous counter (T inputs from the gate networks shown).

Fig: timing diagram (positive-edge clock). Q0 has f/2, Q1 ≈ f/4 (except at the end), Q3 goes high at count 8 and returns to 0 at count 10; the cycle repeats every 10 clock pulses.

11. Sequence detector for 011 using T flip-flops [7]

Assumptions: Mealy machine, overlapping detection allowed. Z = 1 when the last three inputs are 0,1,1.

Step 1 – State diagram

S0: nothing useful received (reset). S1: last bit is 0. S2: last two bits are 01.

Fig: state diagram (edge label = X/Z).

Step 2 – State table and excitation (state code S0 = 00, S1 = 01, S2 = 10; A = MSB; 11 unused)

Step 3 – K-maps (variables A, B, X)

Step 4 – Circuit

Fig: 011 detector – two T flip-flops with common clock; X is the serial input.

12. Main characteristics of digital logic families [4]

1. Propagation delay (t_pd): average time for a change at the input to appear at the output; measures speed.
2. Power dissipation: power consumed by a gate (static + dynamic); lower is better.
3. Speed–power product: t_pd × P; figure of merit (pJ) – smaller is better.
4. Fan-in: maximum number of inputs a gate can have.
5. Fan-out: maximum number of similar gate inputs a gate output can drive without leaving the valid logic levels.
6. Noise margin: maximum noise voltage tolerated without wrong output: NM_H = V_OH(min) − V_IH(min), NM_L = V_IL(max) − V_OL(max).
7. Voltage levels: V_IH, V_IL, V_OH, V_OL and supply voltage V_CC/V_DD.
8. Current parameters: I_IH, I_IL, I_OH, I_OL. Others: operating temperature range, cost, and output type (totem-pole, open-collector, tri-state).