Syllabus map

From Syllabus.pdf (ENEX 152): 45 lecture hours → 60 exam marks. Orange bars are the 10-mark chapters — prioritise these.

Ch1·7 Ch2·4 Ch3·5 Ch4·10 Ch5·7 Ch6·10 Ch7·10 Ch8·7
1. Introduction 5 hrs 7 marks
2. Logic Gates 3 hrs 4 marks
3. Boolean Algebra & K-Maps 4 hrs 5 marks
4. Combinational Logic Circuits 8 hrs 10 marks
5. Sequential Logic Circuits 5 hrs 7 marks
6. Registers and Counters 7 hrs 10 marks
7. Sequential Machine Designs 8 hrs 10 marks
8. Digital Integrated Circuits 5 hrs 7 marks

From the past papers (PQA pic.jpg)

Scanned originals of four TU finals. Always-asked: sequence detector, sync counter, async/ripple counter, shift register + timing, K-map, MUX/encoder/decoder. Open scans beside solved answers.